Product details

Technology Family HCT Supply voltage (Min) (V) 4.5 Supply voltage (Max) (V) 5.5 Number of channels (#) 8 IOL (Max) (mA) 6 IOH (Max) (mA) -6 ICC (Max) (uA) 80 Input type TTL-Compatible CMOS Output type 3-State Features Balanced outputs, Very high speed (tpd 5-10ns), Input clamp diode Rating Catalog
Technology Family HCT Supply voltage (Min) (V) 4.5 Supply voltage (Max) (V) 5.5 Number of channels (#) 8 IOL (Max) (mA) 6 IOH (Max) (mA) -6 ICC (Max) (uA) 80 Input type TTL-Compatible CMOS Output type 3-State Features Balanced outputs, Very high speed (tpd 5-10ns), Input clamp diode Rating Catalog
PDIP (N) 20 229 mm² 24.33 x 9.4 SOIC (DW) 20 132 mm² 12.8 x 10.3 SOP (NS) 20 98 mm² 12.6 x 7.8 TSSOP (PW) 20 42 mm² 6.5 x 6.4
  • Operating Voltage Range of 4.5 V to 5.5 V
  • High-Current Outputs Drive Up To 15
  • LSTTL Loads
  • Low Power Consumption, 80-µA Max ICC
  • Typical tpd = 12 ns
  • ±6-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max
  • Inputs Are TTL-Voltage Compatible
  • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers

  • Operating Voltage Range of 4.5 V to 5.5 V
  • High-Current Outputs Drive Up To 15
  • LSTTL Loads
  • Low Power Consumption, 80-µA Max ICC
  • Typical tpd = 12 ns
  • ±6-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max
  • Inputs Are TTL-Voltage Compatible
  • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers

These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ’HCT240 devices are organized as two 4-bit buffers/drivers with separate output-enable (OE)\ inputs. When (OE)\ is low, the device passes inverted data from the A inputs to the Y outputs. When (OE)\ is high, the outputs are in the high-impedance state.

These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ’HCT240 devices are organized as two 4-bit buffers/drivers with separate output-enable (OE)\ inputs. When (OE)\ is low, the device passes inverted data from the A inputs to the Y outputs. When (OE)\ is high, the outputs are in the high-impedance state.

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Technical documentation

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Type Title Date
* Data sheet SN54HCT240, SN74HCT240 datasheet (Rev. E) 19 Aug 2003
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 01 May 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design & development

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Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, P, N, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
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Limit: 5
Simulation model

SN74HCT240 Behavioral SPICE Model

SCLM199.ZIP (7 KB) - PSpice Model
Package Pins Download
PDIP (N) 20 View options
SO (NS) 20 View options
SOIC (DW) 20 View options
TSSOP (PW) 20 View options

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