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SN74HCT245

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Octal Bus Transceivers With 3-State Outputs

Data sheet
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Octal Bus Transceivers With 3-State Outputs

SN74HCT245

ACTIVE
Data sheet Order now

Product details

Parameters

Technology Family HCT Supply voltage (Min) (V) 4.5 Supply voltage (Max) (V) 5.5 Bits (#) 8 Voltage (Nom) (V) 5 F @ nom voltage (Max) (MHz) 25 ICC @ nom voltage (Max) (mA) 0.08 Propagation delay (Max) (ns) 25 IOL (Max) (mA) 6 IOH (Max) (mA) -6 Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other Standard transceiver

Package | Pins | Size

PDIP (N) 20 229 mm² 24.33 x 9.4 SOIC (DW) 20 132 mm² 12.8 x 10.3 SOP (NS) 20 98 mm² 12.6 x 7.8 SSOP (DB) 20 38 mm² 5.3 x 7.2 TSSOP (PW) 20 42 mm² 6.5 x 6.4 open-in-new Find other Standard transceiver

Features

  • Operating Voltage Range of 4.5 V to 5.5 V
  • High-Current 3-State Outputs Drive Bus Lines Directly or up To 15-LSTTL Loads
  • Low Power Consumption, 80-µA Maximum ICC
  • Typical tpd = 14 ns
  • ±6-mA Output Drive at 5 V
  • Low Input Current of 1 µA Maximum
  • Inputs Are TTL-Voltage Compatible
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Description

The SNx4HCT245 octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.

The SNx4HCT245 devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated.

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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet SNx4HCT245 Octal Bus Transceivers With 3-State Outputs datasheet (Rev. F) Aug. 31, 2016
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
User guide Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application note Designing With Logic (Rev. C) Jun. 01, 1997
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions May 01, 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices
View details

Design tools & simulation

SIMULATION MODEL Download
SCLM097A.ZIP (10 KB) - IBIS Model

CAD/CAE symbols

Package Pins Download
PDIP (N) 20 View options
SO (NS) 20 View options
SOIC (DW) 20 View options
SSOP (DB) 20 View options
TSSOP (PW) 20 View options

Ordering & quality

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  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

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