SN74LS243

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Quad bus transceivers

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Product details

Parameters

Technology Family LS Supply voltage (Min) (V) 4.75 Supply voltage (Max) (V) 5.25 Bits (#) 4 Voltage (Nom) (V) 5 F @ nom voltage (Max) (MHz) 35 ICC @ nom voltage (Max) (mA) 0.05 Propagation delay (Max) (ns) 18 IOL (Max) (mA) 24 IOH (Max) (mA) -15 Rating Catalog Operating temperature range (C) 0 to 70 open-in-new Find other Standard transceiver

Package | Pins | Size

PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6 open-in-new Find other Standard transceiver

Features

  • Two-Way Asynchronous Communication Between Data Buses
  • PNP Inputs Reduce D-C Loading
  • Hysteresis (Typically 400 mV) at Inputs Improves Noise Margin

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Description

These four-data-line transceivers are designed for asynchronous two-way communications between data buses. SN74LS243 can be used to drive terminated lines down to 133 .

SN54LS243 is characterized for operation over the full military temperature range of –55°C to 125°C. SN74LS243 is characterized for operation from 0°C to 70°C.

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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet Quadruple Bus Transceivers datasheet (Rev. A) Jul. 09, 2008
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application note Designing With Logic (Rev. C) Jun. 01, 1997
Application note Designing with the SN54/74LS123 (Rev. A) Mar. 01, 1997
Application note Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application note Live Insertion Oct. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
PDIP (N) 14 View options
SOIC (D) 14 View options

Ordering & quality

Information included:
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  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

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