The SNx4LS24x, SNx4S24x octal buffers and line drivers are designed specifically to improve both the performance and density of three-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The designer has a choice of selected combinations of inverting and non-inverting outputs, symmetrical, active-low output-control (G) inputs, and complementary output-control (G and G) inputs. These devices feature high fan-out, improved fan-in, and 400-mV noise margin. The SN74LS24x and SN74S24x devices can be used to drive terminated lines down to 133 Ω.
| Type | Title | Date | |
|---|---|---|---|
| * | Data sheet | SNx4LS24x, SNx4S24x Octal Buffers and Line Drivers With 3-State Outputs datasheet (Rev. D) | 10 Oct 2016 |
| Selection guide | Logic Guide (Rev. AB) | 12 Jun 2017 | |
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 02 Dec 2015 | |
| User guide | LOGIC Pocket Data Book (Rev. B) | 16 Jan 2007 | |
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 08 Jul 2004 | |
| More literature | Logic Cross-Reference (Rev. A) | 07 Oct 2003 | |
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 29 Aug 2002 | |
| Application note | Designing With Logic (Rev. C) | 01 Jun 1997 | |
| Application note | Designing with the SN54/74LS123 (Rev. A) | 01 Mar 1997 | |
| Application note | Input and Output Characteristics of Digital Integrated Circuits | 01 Oct 1996 | |
| Application note | Live Insertion | 01 Oct 1996 |
For additional terms or required resources, click any title below to view the detail page where available.
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.
| Package | Pins | Download |
|---|---|---|
| PDIP (N) | 20 | View options |
| SO (NS) | 20 | View options |
| SOIC (DW) | 20 | View options |
| SSOP (DB) | 20 | View options |
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