SN74LS26

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Quad 2-input high-voltage interface positive-NAND gates

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Product details

Parameters

Technology Family LS VCC (Min) (V) 4.75 VCC (Max) (V) 5.25 Channels (#) 4 Inputs per channel 2 IOL (Max) (mA) 8 IOH (Max) (mA) -1 Input type Bipolar Output type Push-Pull Features High Speed (tpd 10-50ns) Data rate (Max) (Mbps) 35 Rating Catalog Operating temperature range (C) 0 to 70 open-in-new Find other NAND gate

Package | Pins | Size

PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6 open-in-new Find other NAND gate

Features

  • For Driving Low-Threshold-Voltage MOS Inputs

 

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Description

These 2-input open-collector NAND gates feature high-output voltage ratings for interfacing with low-threshold-voltage MOS logic circuits or other 12-volt systems. Although the output is rated to withstand 15 volts, the VCC terminal is connected to the standard 5-volt source.

The SN5426 and SN54LS26 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN7426 and SN74LS26 are characterized for operation from 0°C to 70°C.

 

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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet Quadruple 2-Input High-Voltage Interface Positive-NAND Gates datasheet Mar. 01, 1988
Technical articles How to keep your motor running safely Jun. 04, 2020
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application note Designing With Logic (Rev. C) Jun. 01, 1997
Application note Designing with the SN54/74LS123 (Rev. A) Mar. 01, 1997
Application note Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application note Live Insertion Oct. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODEL Download
SDLM040.ZIP (6 KB) - PSpice Model

CAD/CAE symbols

Package Pins Download
PDIP (N) 14 View options
SOIC (D) 14 View options

Ordering & quality

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  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

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