SN74LS51

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2-Wide 2-Input and 2-Wide 3-Input AND-OR-Invert Gates

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Product details

Parameters

Technology Family LS VCC (Min) (V) 4.75 VCC (Max) (V) 5.25 Channels (#) 2 Inputs per channel 3 IOL (Max) (mA) 16 Input type Bipolar IOH (Max) (mA) -0.4 Output type Push-Pull Features High Speed (tpd 10-50ns) Data rate (Max) (Mbps) 35 Rating Catalog Operating temperature range (C) 0 to 70 open-in-new Find other Combination gate

Package | Pins | Size

PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6 SOP (NS) 14 80 mm² 10.2 x 7.8 open-in-new Find other Combination gate

Features

  • Package Options Include Plastic “Small Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs
  • Dependable Texas Instruments Quality and Reliability

 

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Description

The '51 and 'S51 contain two independent 2-wide 2-input AND-OR-INVERT gates. They perform the Boolean function Y = AB + CD\.

The 'LS51 contains one 2-wide 3-input and one 2-wide 2-input AND-OR-INVERT gates. They perform the Boolean functions 1Y = (1A · 1B · 1C) + (1D · 1E · 1F)\ and 2Y = (2A · 2B) + (2C · 2D)\.

The SN5451, SN54LS51, and SN54S51 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN7451, SN74LS51 and SN74S51 are characterized for operation from 0°C to 70°C.

 

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Technical documentation

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Type Title Date
* Datasheet AND-OR-Invert Gates datasheet Mar. 01, 1988
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Solution guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Designing with the SN54/74LS123 (Rev. A) Mar. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
$10.00
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
PDIP (N) 14 View options
SO (NS) 14 View options
SOIC (D) 14 View options

Ordering & quality

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