SN74LV04A-Q1

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Automotive Catalog Hex Inverters

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Automotive Catalog Hex Inverters

SN74LV04A-Q1

ACTIVE

Product details

Parameters

Technology Family LV-A VCC (Min) (V) 2 VCC (Max) (V) 5.5 Channels (#) 6 IOL (Max) (mA) 12 IOH (Max) (mA) -12 ICC (Max) (uA) 20 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, Very high speed (tpd 5-10ns), Partial power down (Ioff), Over-voltage tolerant inputs Data rate (Mbps) 220 Rating Automotive open-in-new Find other Inverting buffer/driver

Package | Pins | Size

TSSOP (PW) 14 32 mm² 5 x 6.4 open-in-new Find other Inverting buffer/driver

Features

  • Qualified for Automotive Applications
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 Using Machine Model (C = 200 pF, R = 0)
  • 2-V to 5.5-V VCC Operation
  • Max tpd of 6.5 ns at 5 V
  • Typical VOLP (Output Ground Bounce)
       <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
       >2.3 V at VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on All Ports
  • Ioff Supports Partial-Power-Down Mode Operation

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Description

This hex inverter is designed for 2-V to 5.5-V VCC operation.

The SN74LV04A contains six independent inverters. This device performs the Boolean function Y = A.

The device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 2
Type Title Date
* Datasheet Hex Inverter datasheet (Rev. C) Feb. 07, 2008
More literature Automotive Logic Devices Brochure Aug. 27, 2014

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODEL Download
SCLM193.ZIP (7 KB) - PSpice Model

CAD/CAE symbols

Package Pins Download
TSSOP (PW) 14 View options

Ordering & quality

Information included:
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  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Support & training

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