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Product details

Parameters

Technology Family LV-A VCC (Min) (V) 2 VCC (Max) (V) 5.5 Channels (#) 4 Inputs per channel 2 IOL (Max) (mA) 12 IOH (Max) (mA) -12 Input type Standard CMOS Output type Push-Pull Features Partial Power Down (Ioff), Over-Voltage Tolerant Inputs, Very High Speed (tpd 5-10ns) Data rate (Max) (Mbps) 70 Rating Catalog Operating temperature range (C) -40 to 125, -40 to 85 open-in-new Find other AND gate

Package | Pins | Size

SOIC (D) 14 52 mm² 8.65 x 6 SOP (NS) 14 80 mm² 10.2 x 7.8 SSOP (DB) 14 48 mm² 6.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4 TVSOP (DGV) 14 23 mm² 3.6 x 6.4 VQFN (RGY) 14 12 mm² 3.5 x 3.5 open-in-new Find other AND gate

Features

  • 2-V to 5.5-V VCC Operation
  • Max tpd of 7 ns at 5 V
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    > 2.3 V at VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on
    All Ports
  • Ioff Supports Live Insertion, Partial-Power-Down
    Mode, and Back-Drive Protection
  • Latch-Up Performance Exceeds 250 mA
    Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model
    • 200-V Machine Model
    • 1000-V Charged-Device Model
open-in-new Find other AND gate

Description

This quadruple 2-input positive-AND gate is designed for 2-V to 5.5-V VCC operation. The SN74LV08A device performs the Boolean function Y = A • B or Y = A\ + B\ in positive logic.

open-in-new Find other AND gate
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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 2
Type Title Date
* Datasheet SN74LV08A Quadruple 2-Input Positive-AND Gates datasheet (Rev. M) Oct. 13, 2014
Technical articles How to keep your motor running safely Jun. 04, 2020

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices
EVALUATION BOARD Download
20
Description
Flexible EVM designed to support any logic or translation device that has a BQA, BQB, RGY (14-24 pin), RSV, RJW, or RHL package.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic and translation devices with included dual supply support
  • Board has 9 sections that can be broken apart for a smaller form factor

Design tools & simulation

SIMULATION MODEL Download
SCEM122.ZIP (16 KB) - IBIS Model
SIMULATION MODEL Download
SCEM568.ZIP (1 KB) - PSpice Model
SIMULATION MODEL Download
SCLM190.ZIP (7 KB) - PSpice Model

Reference designs

REFERENCE DESIGNS Download
Bidirectional RS-485 Fan-Out Hub Reference Design
TIDA-01365 — The Bidirectional RS-485 Fan-Out Hub Reference Design (TIDA-01365) documents and tests an RS-485 fan-out hub design where 1:N and N:1 RS-485 signals are aggregated in and out of any bus topology. This design also features automatic direction control, for reduced pin count on microcontrollers, and a (...)
document-generic Schematic

CAD/CAE symbols

Package Pins Download
SO (NS) 14 View options
SOIC (D) 14 View options
SSOP (DB) 14 View options
TSSOP (PW) 14 View options
TVSOP (DGV) 14 View options
VQFN (RGY) 14 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Support & training

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