SN74LV11A-EP Enhanced Product Triple 3-Input Positive-And Gates | TI.com

SN74LV11A-EP (ACTIVE) Enhanced Product Triple 3-Input Positive-And Gates

Enhanced Product Triple 3-Input Positive-And Gates - SN74LV11A-EP
Datasheet
 

Description

This triple 3-input positive-AND gate is designed for 2-V to 5.5-V VCC operation.

The SN74LV11A performs the Boolean function Y = A • B • C or Y = (A\ + B\ + C\)\ in positive logic.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Features

  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Extended Temperature Performance of –40°C to 105°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree
  • 2-V to 5.5-V VCC Operation
  • Typical VOLP (Output Ground Bounce)
       <0.8 V at VCC= 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
       >2.3 V at VCC = 3.3 V, TA = 25°C
  • Supports Mixed-Mode Voltage Operation on All Ports
  • Ioff Supports Partial-Power-Down Mode Operation

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

Parametrics

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Part number Order Technology Family VCC (Min) (V) VCC (Max) (V) Channels (#) Inputs per channel IOL (Max) (mA) IOH (Max) (mA) Input type Output type Features Data rate (Max) (Mbps) Rating Operating temperature range (C) Package size: mm2:W x L (PKG) Package Group
SN74LV11A-EP Order now LV-A     2     5.5     3     3     12     -12     Standard CMOS     Push-Pull     Partial Power Down (Ioff)
Over-Voltage Tolerant Inputs
Very High Speed (tpd 5-10ns)    
70     HiRel Enhanced Product     -40 to 105     14TSSOP: 32 mm2: 6.4 x 5 (TSSOP | 14)     TSSOP | 14    
SN74LV11A Order now LV-A     2     5.5     3     3     12     -12     Standard CMOS     Push-Pull     Partial Power Down (Ioff)
Over-Voltage Tolerant Inputs
Very High Speed (tpd 5-10ns)    
70     Catalog     -40 to 85     14SO: 80 mm2: 7.8 x 10.2 (SO | 14)
14SOIC: 52 mm2: 6 x 8.65 (SOIC | 14)
14SSOP: 48 mm2: 7.8 x 6.2 (SSOP | 14)
14TSSOP: 32 mm2: 6.4 x 5 (TSSOP | 14)
14TVSOP: 23 mm2: 6.4 x 3.6 (TVSOP | 14)    
SOIC | 14
SO | 14
SSOP | 14
TSSOP | 14
TVSOP | 14    
SN74LV11A-Q1 Samples not available LV-A     2     5.5     3     3     12     -12     Standard CMOS     Push-Pull     Partial Power Down (Ioff)
Over-Voltage Tolerant Inputs
Very High Speed (tpd 5-10ns)    
70     Automotive     -40 to 105     14TSSOP: 32 mm2: 6.4 x 5 (TSSOP | 14)     TSSOP | 14