SN74LV11A-EP

ACTIVE

Enhanced product 3-ch, 3-input, 2-V to 5.5-V AND gates

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Enhanced product 3-ch, 3-input, 2-V to 5.5-V AND gates

SN74LV11A-EP

ACTIVE

Product details

Parameters

Technology Family LV-A Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 5.5 Channels (#) 3 Inputs per channel 3 IOL (Max) (mA) 12 IOH (Max) (mA) -12 Input type Standard CMOS Output type Push-Pull Features Partial power down (Ioff), Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Data rate (Max) (Mbps) 70 Rating HiRel Enhanced Product Operating temperature range (C) -40 to 105 open-in-new Find other AND gate

Package | Pins | Size

TSSOP (PW) 14 32 mm² 5 x 6.4 open-in-new Find other AND gate

Features

  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Extended Temperature Performance of –40°C to 105°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree
  • 2-V to 5.5-V VCC Operation
  • Typical VOLP (Output Ground Bounce)
       <0.8 V at VCC= 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
       >2.3 V at VCC = 3.3 V, TA = 25°C
  • Supports Mixed-Mode Voltage Operation on All Ports
  • Ioff Supports Partial-Power-Down Mode Operation

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

open-in-new Find other AND gate

Description

This triple 3-input positive-AND gate is designed for 2-V to 5.5-V VCC operation.

The SN74LV11A performs the Boolean function Y = A • B • C or Y = (A\ + B\ + C\)\ in positive logic.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

open-in-new Find other AND gate
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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 3
Type Title Date
* Datasheet SN74LV11A-EP datasheet (Rev. A) May 11, 2004
* VID SN74LV11A-EP VID V6204692 Jun. 21, 2016
Technical articles How to keep your motor running safely Jun. 04, 2020

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

CAD/CAE symbols

Package Pins Download
TSSOP (PW) 14 View options

Ordering & quality

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