The SN74LV125AT is a quadruple bus buffer gate. This device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
|Part number||Order||Technology Family||VCC (Min) (V)||VCC (Max) (V)||Channels (#)||IOL (Max) (mA)||IOH (Max) (mA)||ICC (uA)||Input type||Output type||Features||Data rate (Mbps)||Rating||Package Group|
Very high speed (tpd 5-10ns)
Partial power down (Ioff)
Over-voltage tolerant inputs
SOIC | 14
SO | 14
SSOP | 14
TSSOP | 14
VQFN | 14