Product details

Technology family LV-AT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 4 IOL (max) (mA) 16 Supply current (max) (µA) 20 IOH (max) (mA) -16 Input type TTL-Compatible CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 85
Technology family LV-AT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 4 IOL (max) (mA) 16 Supply current (max) (µA) 20 IOH (max) (mA) -16 Input type TTL-Compatible CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 14 51.9 mm² 8.65 x 6 SOP (NS) 14 79.56 mm² 10.2 x 7.8 SSOP (DB) 14 48.36 mm² 6.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4 VQFN (RGY) 14 12.25 mm² 3.5 x 3.5
  • Inputs Are TTL-Voltage Compatible
  • 4.5-V to 5.5-V V CC Operation
  • Typical t pd of 3.8 ns at 5 V
  • Typical V OLP (Output Ground Bounce) < 0.8 V at V CC = 5 V, T A = 25°C
  • Typical V OHV (Output V OH Undershoot) > 2.3 V at V CC = 5 V, T A = 25°C
  • Support Mixed-Mode Voltage Operation on All Ports
  • I off Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • Inputs Are TTL-Voltage Compatible
  • 4.5-V to 5.5-V V CC Operation
  • Typical t pd of 3.8 ns at 5 V
  • Typical V OLP (Output Ground Bounce) < 0.8 V at V CC = 5 V, T A = 25°C
  • Typical V OHV (Output V OH Undershoot) > 2.3 V at V CC = 5 V, T A = 25°C
  • Support Mixed-Mode Voltage Operation on All Ports
  • I off Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17

The SN74LV125AT is a quadruple bus buffer gate. This device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable ( OE) input is high.

The SN74LV125AT is a quadruple bus buffer gate. This device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable ( OE) input is high.

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Technical documentation

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* Data sheet SN74LV125AT Quadruple Bus Buffer Gates With 3-State Outputs datasheet (Rev. B) PDF | HTML 14 Jul 2023

Design & development

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Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
Not available on TI.com
Evaluation board

14-24-NL-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin non-leaded packages

14-24-NL-LOGIC-EVM is a flexible evaluation module (EVM) designed to support any logic or translation device that has a 14-pin to 24-pin BQA, BQB, RGY, RSV, RJW or RHL package.

User guide: PDF | HTML
Not available on TI.com
Simulation model

SN74LV125AT Behavioral SPICE Model

SCEM655.ZIP (7 KB) - PSpice Model
Package Pins Download
SOIC (D) 14 View options
SOP (NS) 14 View options
SSOP (DB) 14 View options
TSSOP (PW) 14 View options
VQFN (RGY) 14 View options

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