4-ch, 4-input, 2-V to 5.5-V NAND gates with Schmitt-Trigger inputs


Product details


Technology Family LV-A Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 5.5 Number of channels (#) 4 Inputs per channel 4 IOL (Max) (mA) 12 IOH (Max) (mA) -12 Input type Schmitt-Trigger Output type Push-Pull Features Partial power down (Ioff), Over-voltage tolerant inputs, High speed (tpd 10- 50ns) Data rate (Max) (Mbps) 70 Rating Catalog open-in-new Find other NAND gate

Package | Pins | Size

SOIC (D) 14 52 mm² 8.65 x 6 SOP (NS) 14 80 mm² 10.2 x 7.8 SSOP (DB) 14 48 mm² 6.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4 TVSOP (DGV) 14 23 mm² 3.6 x 6.4 open-in-new Find other NAND gate


  • 2-V to 5.5-V VCC Operation
  • Max tpd of 9 ns at 5 V
  • Typical VOLP (Output Ground Bounce) <0.8 V at
    VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) >2.3 V at
    VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on All
  • Latch-Up Performance Exceeds 250 mA per
    JESD 17
  • Ioff Supports Live Insertion, Partial Power-Down
    Mode, and Back Drive Protection
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
    • Industrial PC: Rugged PC and Laptop
    • Access Control and Security: Camera
      Surveillance IP Network
    • Vending, Payment and Change Machines
    • Patient Monitoring STB / DVR / Streaming Media
    • Other Motor Drives (Such as Switch Reluctance)

All other trademarks are the property of their respective owners

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The ’LV132A devices are quadruple positive-NAND gates designed for 2-V to 5.5-V VCC operation.

The ’LV132A devices perform the Boolean function Y = A • B or Y = A + B in positive logic.

Each circuit functions as a NAND gate, but because of the Schmitt trigger, it has different input threshold levels for positive- and negative-going signals.

These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give clean jitter-free output signals.

open-in-new Find other NAND gate

Technical documentation

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Type Title Date
* Data sheet SNx4LV132A Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs datasheet (Rev. J) Feb. 20, 2015
Technical article How to keep your motor running safely Jun. 04, 2020

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

document-generic User guide
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SCEJ153.ZIP (51 KB) - HSpice Model
SCEM128A.ZIP (36 KB) - IBIS Model
SCLM188.ZIP (7 KB) - PSpice Model

CAD/CAE symbols

Package Pins Download
SO (NS) 14 View options
SOIC (D) 14 View options
SSOP (DB) 14 View options
TSSOP (PW) 14 View options
TVSOP (DGV) 14 View options

Ordering & quality

Information included:
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  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Support & training

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