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SN74LV1T04-Q1

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Automotive single power supply inverter gate logic level shifter

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Data sheet

SN74LV1T04-Q1

ACTIVE
Data sheet Order now

Product details

Technology family LV1T Applications GPIO, SPI Bits (#) 1 Configuration 1 Ch A to B 0 Ch B to A High input voltage (min) (V) 1 High input voltage (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Data rate (max) (Mbps) 100 IOH (max) (mA) -8 IOL (max) (mA) 8 Features Balanced outputs, Single supply Input type TTL-Compatible CMOS Output type Balanced CMOS, Push-Pull Rating Automotive Operating temperature range (°C) -40 to 125
Technology family LV1T Applications GPIO, SPI Bits (#) 1 Configuration 1 Ch A to B 0 Ch B to A High input voltage (min) (V) 1 High input voltage (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Data rate (max) (Mbps) 100 IOH (max) (mA) -8 IOL (max) (mA) 8 Features Balanced outputs, Single supply Input type TTL-Compatible CMOS Output type Balanced CMOS, Push-Pull Rating Automotive Operating temperature range (°C) -40 to 125
SOT-23 (DBV) 5 8.12 mm² 2.9 x 2.8 SOT-SC70 (DCK) 5 4.2 mm² 2 x 2.1

  • AEC-Q100 qualified for automotive applications:

    • Device temperature grade 1: -40°C to +125°C
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C4B
  • Wide operating range of 1.8 V to 5.5 V
  • Single-supply voltage translator (refer to LVxT Enhanced Input Voltage):
    • Up translation:
      • 1.2 V to 1.8 V
      • 1.5 V to 2.5 V
      • 1.8 V to 3.3 V
      • 3.3 V to 5.0 V
    • Down translation:
      • 5.0 V, 3.3 V, 2.5 V to 1.8 V
      • 5.0 V, 3.3 V to 2.5 V
      • 5.0 V to 3.3 V
  • 5.5-V tolerant input pins
  • Supports standard pinouts
  • Up to 150Mbps with 5-V or 3.3-V V CC
  • Latch-up performance exceeds 250 mA per JESD 17

  • AEC-Q100 qualified for automotive applications:

    • Device temperature grade 1: -40°C to +125°C
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C4B
  • Wide operating range of 1.8 V to 5.5 V
  • Single-supply voltage translator (refer to LVxT Enhanced Input Voltage):
    • Up translation:
      • 1.2 V to 1.8 V
      • 1.5 V to 2.5 V
      • 1.8 V to 3.3 V
      • 3.3 V to 5.0 V
    • Down translation:
      • 5.0 V, 3.3 V, 2.5 V to 1.8 V
      • 5.0 V, 3.3 V to 2.5 V
      • 5.0 V to 3.3 V
  • 5.5-V tolerant input pins
  • Supports standard pinouts
  • Up to 150Mbps with 5-V or 3.3-V V CC
  • Latch-up performance exceeds 250 mA per JESD 17

The SN74LV1T04-Q1 contains a single buffer gate with integrated voltage level translation. Each gate performs the Boolean function Y = A in positive logic. The output level is referenced to the supply voltage (V CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).

The SN74LV1T04-Q1 contains a single buffer gate with integrated voltage level translation. Each gate performs the Boolean function Y = A in positive logic. The output level is referenced to the supply voltage (V CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).
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* Data sheet SN74LV1T04-Q1 AutomotiveSingle Inverter Gate with Integrated Translation datasheet (Rev. A) PDF | HTML 16 Nov 2023

Design & development

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Evaluation board

5-8-LOGIC-EVM — Generic logic evaluation module for 5-pin to 8-pin DCK, DCT, DCU, DRL and DBV packages

Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
User guide: PDF
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Package Pins Download
SOT-23 (DBV) 5 View options
SOT-SC70 (DCK) 5 View options
TI's Standard Terms and Conditions for Evaluation Items apply.

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