SN74LV21A Dual 4-Input Positive-AND Gate | TI.com

SN74LV21A (ACTIVE)

Dual 4-Input Positive-AND Gate

Dual 4-Input Positive-AND Gate - SN74LV21A
Datasheet
 

Description

These dual 4-input positive-AND gates are designed for 2-V to 5.5-V VCC operation.

The 'LV21A devices perform the Boolean function Y = A • B 1 C • D or Y = (A\ + B\ + C\ + D\)\ in positive logic.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

Features

  • 2-V to 5.5-V VCC Operation
  • Max tpd of 6 ns at 5 V
  • Typical VOLP (Output Ground Bounce)
        <0.8 V at VCC, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
       >2.3 V at VCC, TA = 25°C
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

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Parametrics Compare all products in AND gate

 
Technology Family
VCC (Min) (V)
VCC (Max) (V)
Channels (#)
Inputs per channel
IOL (Max) (mA)
IOH (Max) (mA)
Input type
Output type
Features
Data rate (Max) (Mbps)
Rating
Operating temperature range (C)
Package Group
Package size: mm2:W x L (PKG)
SN74LV21A
LV-A    
2    
5.5    
2    
4    
12    
-12    
Standard CMOS    
Push-Pull    
Partial Power Down (Ioff)
Over-Voltage Tolerant Inputs
Very High Speed (tpd 5-10ns)    
70    
Catalog    
-40 to 85    
SOIC | 14
SO | 14
SSOP | 14
TSSOP | 14
TVSOP | 14    
14SO: 80 mm2: 7.8 x 10.2 (SO | 14)
14SOIC: 52 mm2: 6 x 8.65 (SOIC | 14)
14SSOP: 48 mm2: 7.8 x 6.2 (SSOP | 14)
14TSSOP: 32 mm2: 6.4 x 5 (TSSOP | 14)
14TVSOP: 23 mm2: 6.4 x 3.6 (TVSOP | 14)