These octal buffers/drivers with inverted outputs are designed for 2-V to 5.5-V VCC operation.
The LV240A devices are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
These devices are organized as two 4-bit buffers/line drivers with separate output-enable (OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.
|Part number||Order||Technology Family||VCC (Min) (V)||VCC (Max) (V)||Channels (#)||IOL (Max) (mA)||IOH (Max) (mA)||ICC (uA)||Input type||Output type||Features||Data rate (Mbps)||Rating||Package Group|
Very high speed (tpd 5-10ns)
Partial power down (Ioff)
Over-voltage tolerant inputs
SOIC | 20
SO | 20
SSOP | 20
TSSOP | 20
TVSOP | 20