SN74LVC02A Quadruple 2-Input Positive-NOR Gate | TI.com

SN74LVC02A (ACTIVE) Quadruple 2-Input Positive-NOR Gate

Quadruple 2-Input Positive-NOR Gate - SN74LVC02A
Datasheet
 

Description

The SN54LVC02A quadruple 2-input positive-NOR gate is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC02A quadruple 2-input positive-NOR gate is designed for 1.65-V to 3.6-V VCC operation.

The 'LVC02A devices perform the Boolean function Y = A + B or Y = AB in positive logic.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.

Features

  • Operate From 1.65 V to 3.6 V
  • Specified From -40°C to 85°C, -40°C to 125°C, and -55°C to 125°C
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.4 ns at 3.3 V
  • Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Parametrics

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Part number Order Technology Family VCC (Min) (V) VCC (Max) (V) Channels (#) Inputs per channel IOL (Max) (mA) IOH (Max) (mA) Input type Output type Features Data rate (Max) (Mbps) Rating Operating temperature range (C) Package size: mm2:W x L (PKG) Package Group
SN74LVC02A Order now LVC     1.5     3.6     4     2     24     -24     Standard CMOS     Push-Pull     Partial Power Down (Ioff)
Over-Voltage Tolerant Inputs
Ultra High Speed (tpd <5ns)    
100       -40 to 125     14SO: 80 mm2: 7.8 x 10.2 (SO | 14)
14SOIC: 52 mm2: 6 x 8.65 (SOIC | 14)
14SSOP: 48 mm2: 7.8 x 6.2 (SSOP | 14)
14TSSOP: 32 mm2: 6.4 x 5 (TSSOP | 14)
14VQFN: 12 mm2: 3.5 x 3.5 (VQFN | 14)    
SOIC | 14
SO | 14
SSOP | 14
TSSOP | 14
VQFN | 14    
SN54LVC02A Samples not available LVC     2     3.6     4     2     24     -24     Standard CMOS     Push-Pull     Partial Power Down (Ioff)
Over-Voltage Tolerant Inputs
Ultra High Speed (tpd <5ns)    
100     Military     -55 to 125     See datasheet (CDIP)
See datasheet (CFP)
20LCCC: 79 mm2: 8.89 x 8.89 (LCCC | 20)    
CDIP | 14
CFP | 14
LCCC | 20    
SN74LVC02A-EP Samples not available LVC     2     3.6     4     2     24     -24     Standard CMOS     Push-Pull     Partial Power Down (Ioff)
Over-Voltage Tolerant Inputs
Ultra High Speed (tpd <5ns)    
100     HiRel Enhanced Product     -55 to 125     14TSSOP: 32 mm2: 6.4 x 5 (TSSOP | 14)     TSSOP | 14    
SN74LVC02A-Q1 Samples not available LVC     2     3.6     4     2     24     -24     Standard CMOS     Push-Pull     Partial Power Down (Ioff)
Over-Voltage Tolerant Inputs
Very High Speed (tpd 5-10ns)    
100     Automotive     -40 to 125     14SOIC: 52 mm2: 6 x 8.65 (SOIC | 14)
14TSSOP: 32 mm2: 6.4 x 5 (TSSOP | 14)    
SOIC | 14
TSSOP | 14