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SN74LVC08A

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4-ch, 2-input, 1.65-V to 3.6-V AND gates

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Data sheet
4-ch, 2-input, 1.65-V to 3.6-V AND gates

SN74LVC08A

ACTIVE
Data sheet Order now

Product details

Technology Family LVC Supply voltage (Min) (V) 1.65 Supply voltage (Max) (V) 3.6 Number of channels (#) 4 Inputs per channel 2 IOL (Max) (mA) 24 IOH (Max) (mA) -24 Input type Standard CMOS Output type Push-Pull Features Partial power down (Ioff), Over-voltage tolerant inputs, Ultra high speed (tpd <5ns) Data rate (Max) (Mbps) 100 Rating Catalog Operating temperature range (C) -40 to 125
Technology Family LVC Supply voltage (Min) (V) 1.65 Supply voltage (Max) (V) 3.6 Number of channels (#) 4 Inputs per channel 2 IOL (Max) (mA) 24 IOH (Max) (mA) -24 Input type Standard CMOS Output type Push-Pull Features Partial power down (Ioff), Over-voltage tolerant inputs, Ultra high speed (tpd <5ns) Data rate (Max) (Mbps) 100 Rating Catalog Operating temperature range (C) -40 to 125
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SOIC (D) 14 52 mm² 8.65 x 6 SOP (NS) 14 80 mm² 10.2 x 7.8 SSOP (DB) 14 48 mm² 6.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4 VQFN (RGY) 14 12 mm² 3.5 x 3.5
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  • Latch-Up Performance Exceeds 250 mA
    Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
    • On Products Compliant to MIL-PRF-38535,
      All Parameters Are Tested Unless Otherwise Noted. On All Other Products, Production Processing Does Not Necessarily Include Testing of All Parameters.
  • SN74LVC04A Operates From 1.65 V to 3.6 V
  • SN54LVC04A Operates From 2.0 V to 3.6 V
  • SNx4LVC08A Specified From –40°C to +85°C and –40°C to +125°C
  • SN54LVC08A Specified From –55°C to +125°C
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.1 ns at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Latch-Up Performance Exceeds 250 mA
    Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
    • On Products Compliant to MIL-PRF-38535,
      All Parameters Are Tested Unless Otherwise Noted. On All Other Products, Production Processing Does Not Necessarily Include Testing of All Parameters.
  • SN74LVC04A Operates From 1.65 V to 3.6 V
  • SN54LVC04A Operates From 2.0 V to 3.6 V
  • SNx4LVC08A Specified From –40°C to +85°C and –40°C to +125°C
  • SN54LVC08A Specified From –55°C to +125°C
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.1 ns at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
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The SN54LVC08A quadruple 2-input positive-AND gate is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC08A quadruple 2-input positive-AND gate is designed for 1.65-V to 3.6-V VCC operation.

The SNx4LVC08A devices perform the Boolean function in positive logic.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.

The SN54LVC08A quadruple 2-input positive-AND gate is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC08A quadruple 2-input positive-AND gate is designed for 1.65-V to 3.6-V VCC operation.

The SNx4LVC08A devices perform the Boolean function in positive logic.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.

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Technical documentation

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Type Title Date
* Data sheet SNx4LVC08A Quadruple 2-Input Positive-AND Gates datasheet (Rev. T) 17 Apr 2017
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
More literature Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 06 Nov 2003
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 18 Dec 2002
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 Jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 May 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 May 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 27 Mar 2002
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note LVC Characterization Information 01 Dec 1996
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Design guide Low-Voltage Logic (LVC) Designer's Guide 01 Sep 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 May 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, DYY, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.

document-pdfAcrobat User guide
In stock
Limit: 5
Evaluation board

14-24-NL-LOGIC-EVM — Generic 14 through 24 pin non-leaded package evaluation module

Flexible EVM designed to support any logic or translation device that has a BQA, BQB, RGY (14-24 pin), RSV, RJW, or RHL package.
document-pdfAcrobat User guide
In stock
Limit: 10
Simulation model

SN74LVC08A Behavioral SPICE Model

SCAM114.ZIP (7 KB) - PSpice Model
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Simulation model

SN74LVC08A IBIS Model (Rev. A)

SCEM010A.ZIP (35 KB) - IBIS Model
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Package Pins Download
SO (NS) 14 View options
SOIC (D) 14 View options
SSOP (DB) 14 View options
TSSOP (PW) 14 View options
VQFN (RGY) 14 View options

Ordering & quality

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