SN74LVC125A

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Quadruple Bus Buffer Gate With 3-State Outputs

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Product details

Parameters

Technology Family LVC VCC (Min) (V) 1.65 VCC (Max) (V) 3.6 Channels (#) 4 IOL (Max) (mA) 24 IOH (Max) (mA) -24 Input type Standard CMOS Output type 3-State Features Balanced outputs, Very high speed (tpd 5-10ns), Over-voltage tolerant inputs Data rate (Mbps) 200 Rating Catalog open-in-new Find other Non-Inverting buffer/driver

Package | Pins | Size

SOIC (D) 14 52 mm² 8.65 x 6 SOP (NS) 14 80 mm² 10.2 x 7.8 SSOP (DB) 14 48 mm² 6.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4 VQFN (RGY) 14 12 mm² 3.5 x 3.5 open-in-new Find other Non-Inverting buffer/driver

Features

  • 3-State Outputs
  • Separate OE for all 4 buffers
  • Operates From 1.65 V to 3.6 V
  • Specified From –40°C to 85°C
    and –40°C to 125°C
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.8 ns at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    > 2 V at VCC = 3.3 V, TA = 25°C
  • Latch-Up Performance Exceeds 250 mA
    Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model
    • 200-V Machine Model
    • 1000-V Charged-Device Model
  • APPLICATIONS
    • Cable Modem Termination Systems
    • IP Phones: Wired and Wireless
    • Optical Modules
    • Optical Networking:
      • EPON or Video Over Fiber
    • Point-to-Point Microwave Backhaul
    • Power: Telecom DC/DC Modules:
      • Analog or Digital
    • Private Branch Exchanges (PBX)
    • TETRA Base Stations
    • Telecom Base Band Units
    • Telecom Shelters:
      • Filter Units
      • Power Distribution Units (PDU)
      • Power Monitoring Units (PMU)
      • Wireless Battery Monitoring
      • Remote Electrical Tilt Units (RET)
      • Remote Radio Units (RRU)
      • Tower Mounted Amplifiers (TMA)
    • Vector Signal Analyzers and Generators
    • Video Conferencing: IP-Based HD
    • WiMAX and Wireless Infrastructure Equipment
    • Wireless Communications Testers
    • xDSL Modems and DSLAM

All other trademarks are the property of their respective owners

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Description

This quadruple bus buffer gate is designed for 1.65-V to 3.6-V VCC operation.

The SN74LVC125A device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.

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Technical documentation

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Type Title Date
* Datasheet SN74LVC125A Quadruple Bus Buffer Gate With 3-State Outputs datasheet (Rev. Q) Jan. 25, 2015
Selection guides Little Logic Guide 2018 (Rev. G) Jul. 06, 2018
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes How to Select Little Logic (Rev. A) Jul. 26, 2016
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
More literature Design Summary for WCSP Little Logic (Rev. B) Nov. 04, 2004
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application notes Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
User guides Signal Switch Data Book (Rev. A) Nov. 14, 2003
Application notes Use of the CMOS Unbuffered Inverter in Oscillator Circuits Nov. 06, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
User guides LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) Dec. 18, 2002
Application notes Texas Instruments Little Logic Application Report Nov. 01, 2002
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards Jun. 13, 2002
Application notes 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) May 22, 2002
Application notes Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices May 10, 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS Mar. 27, 2002
More literature Military Low Voltage Solutions Apr. 04, 2001
Application notes Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices Dec. 01, 1997
Application notes Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes LVC Characterization Information Dec. 01, 1996
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996
User guides Low-Voltage Logic (LVC) Designer's Guide Sep. 01, 1996
Application notes Understanding Advanced Bus-Interface Products Design Guide May 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
$10.00
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODELS Download
SCAM059.ZIP (30 KB) - PSpice Model
SIMULATION MODELS Download
SCAM060.ZIP (44 KB) - TINA-TI Reference Design
SIMULATION MODELS Download
SCAM061.ZIP (9 KB) - TINA-TI Spice Model
SIMULATION MODELS Download
SCAM111.ZIP (7 KB) - PSpice Model
SIMULATION MODELS Download
SCEJ248.ZIP (97 KB) - HSpice Model
SIMULATION MODELS Download
SCEM013C.ZIP (45 KB) - IBIS Model

Reference designs

REFERENCE DESIGNS Download
Isolated Loop Powered Thermocouple Transmitter Reference Design
TIDA-00189 The Isolated Loop powered Thermocouple Transmitter reference design is a system solution providing precision K-type thermocouple measurements for 4 to 20-mA isolated current-loop applications. This design is intended as an evaluation module for users to fast prototype and develop end-products for (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
SO (NS) 14 View options
SOIC (D) 14 View options
SSOP (DB) 14 View options
TSSOP (PW) 14 View options
VQFN (RGY) 14 View options

Ordering & quality

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