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SN74LVC125A

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Four-channel 1.65V-to-3.6V buffers with 3-state outputs

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Data sheet

SN74LVC125A

ACTIVE
Data sheet Order now

Product details

Technology family LVC Number of channels 4 IOL (max) (mA) 24 Supply current (max) (µA) 40 IOH (max) (mA) -24 Input type Standard CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LVC Number of channels 4 IOL (max) (mA) 24 Supply current (max) (µA) 40 IOH (max) (mA) -24 Input type Standard CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
TSSOP (PW) 14 32 mm² (5 mm × 6.4 mm) SOP (NS) 14 79.56 mm² (10.2 mm × 7.8 mm) SOIC (D) 14 51.9 mm² (8.65 mm × 6 mm) VQFN (RGY) 14 12.25 mm² (3.5 mm × 3.5 mm) SSOP (DB) 14 48.36 mm² (6.2 mm × 7.8 mm) WQFN (BQA) 14 7.5 mm² (3 mm × 2.5 mm)
  • 3-State outputs
  • Separate OE for all 4 buffers
  • Operates from 1.65V to 3.6V
  • Specified from –40°C to 85°C and –40°C to 125°C
  • Inputs accept voltages to 5.5V
  • Max tpd of 4.8ns at 3.3V
  • Typical VOLP (output ground bounce) < 0.8V at VCC = 3.3V, TA = 25°C
  • Typical VOHV (output VOH undershoot) > 2V at VCC = 3.3V, TA = 25°C
  • Latch-up performance exceeds 250mA per JESD 17
  • 3-State outputs
  • Separate OE for all 4 buffers
  • Operates from 1.65V to 3.6V
  • Specified from –40°C to 85°C and –40°C to 125°C
  • Inputs accept voltages to 5.5V
  • Max tpd of 4.8ns at 3.3V
  • Typical VOLP (output ground bounce) < 0.8V at VCC = 3.3V, TA = 25°C
  • Typical VOHV (output VOH undershoot) > 2V at VCC = 3.3V, TA = 25°C
  • Latch-up performance exceeds 250mA per JESD 17

This quadruple bus buffer gate is designed for 1.65V to 3.6V VCC operation.

The SN74LVC125A device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V system environment.

This quadruple bus buffer gate is designed for 1.65V to 3.6V VCC operation.

The SN74LVC125A device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V system environment.
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet SN74LVC125A Quadruple Bus Buffer Gate With 3-State Outputs datasheet (Rev. T) PDF | HTML Sep 6, 2024
Application brief Optimizing Optical Network Terminal Units With Logic PDF | HTML Apr 5, 2023
Application brief Optimizing Board Space for Discrete LOGIC Designs Using Smallest Package Solutio (Rev. A) PDF | HTML Sep 29, 2022

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

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Evaluation board

14-24-NL-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin non-leaded packages

14-24-NL-LOGIC-EVM is a flexible evaluation module (EVM) designed to support any logic or translation device that has a 14-pin to 24-pin BQA, BQB, RGY, RSV, RJW or RHL package.

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Simulation model

HSPICE Model for SN74LVC125A

SCEJ248.ZIP (97 KB) - HSpice model
Supported products & hardware
Simulation model

SN74LVC125A Behavioral SPICE Model

SCAM111.ZIP (7 KB) - PSpice model
Supported products & hardware
Simulation model

SN74LVC125A IBIS Model (Rev. C)

SCEM013C.ZIP (45 KB) - IBIS model
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Simulation model

SN74LVC125A PSpice Transient Model

SCAM059.ZIP (30 KB) - PSpice model
Supported products & hardware
Simulation model

SN74LVC125A TINA-TI Transient Reference Design

SCAM060.ZIP (44 KB) - TINA-TI reference design
Supported products & hardware
Simulation model

SN74LVC125A TINA-TI Transient Spice Model

SCAM061.ZIP (9 KB) - TINA-TI Spice model
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Reference design

TIDA-00189 — Isolated Loop Powered Thermocouple Transmitter Reference Design

The Isolated Loop powered Thermocouple Transmitter reference design is a system solution providing precision K-type thermocouple measurements for 4 to 20-mA isolated current-loop applications. This design is intended as an evaluation module for users to fast prototype and develop end-products for (...)

Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
TSSOP (PW) 14 Ultra Librarian
SOP (NS) 14 Ultra Librarian
SOIC (D) 14 Ultra Librarian
VQFN (RGY) 14 Ultra Librarian
SSOP (DB) 14 Ultra Librarian
WQFN (BQA) 14 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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