This quadruple bus buffer gate is designed for 1.65-V to 3.6-V VCC
operation.
The SN74LVC125A device features independent line drivers with 3-state outputs. Each
output is disabled when the associated output-enable (OE) input is
high.
To ensure the high-impedance state during power up or power down,
OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the
driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of
this device as a translator in a mixed 3.3-V/5-V system environment.
This quadruple bus buffer gate is designed for 1.65-V to 3.6-V VCC
operation.
The SN74LVC125A device features independent line drivers with 3-state outputs. Each
output is disabled when the associated output-enable (OE) input is
high.
To ensure the high-impedance state during power up or power down,
OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the
driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of
this device as a translator in a mixed 3.3-V/5-V system environment.