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16-Bit Dual-Supply Bus Transceiver, Configurable Voltage Translation, 3-State Outputs

SN74LVCH16T245

ACTIVE

Product details

Parameters

Technology Family LVC Bits (#) 16 High input voltage (Min) (Vih) 1.08 High input voltage (Max) (Vih) 5.5 Output voltage (Min) (V) 1.65 Output voltage (Max) (V) 5.5 IOH (Max) (mA) -32 IOL (Max) (mA) 32 Rating Catalog open-in-new Find other Direction-controlled voltage translators

Package | Pins | Size

SSOP (DL) 48 164 mm² 15.88 x 10.35 TSSOP (DGG) 48 101 mm² 12.5 x 8.1 TVSOP (DGV) 48 62 mm² 9.7 x 6.4 open-in-new Find other Direction-controlled voltage translators

Features

  • Control Inputs VIH/VIL Levels are Referenced to
    VCCA Voltage
  • VCC Isolation Feature – If Either VCC Input is at
    GND, All Outputs are in the High-Impedance State
  • Overvoltage-Tolerant Inputs and Outputs Allow
    Mixed-Voltage-Mode Data Communications
  • Fully Configurable Dual-Rail Design Allows Each
    Port to Operate Over the Full 1.65 V to 5.5 V
    Power-Supply Range
  • Bus Hold on Data Inputs Eliminates the Need for
    External Pullup and Pulldown Resistors
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II
  • ESD Protection Exceeds JESD 22
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Description

This 16-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.

The SN74LVCH16T245 device control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by VCCA.

The SN74LVCH16T245 device is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

Active bus-hold circuitry holds unused or undriven data inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. The bus-hold circuitry on the powered-up side always stays active.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature ensures that if either VCC input is at GND, then all outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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Technical documentation

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Type Title Date
* Datasheet SN74LVCH16T245 16-bit Dual-supply Bus Transceiver With Configurable Level-Shifting/Voltage Translation and Tri-State Outputs datasheet (Rev. B) Apr. 28, 2015
Selection guide Voltage translation buying guide Jun. 13, 2019
Selection guide Little Logic Guide 2018 (Rev. G) Jul. 06, 2018
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note How to Select Little Logic (Rev. A) Jul. 26, 2016
Application note Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
More literature Design Summary for WCSP Little Logic (Rev. B) Nov. 04, 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application note Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
User guide Signal Switch Data Book (Rev. A) Nov. 14, 2003
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits Nov. 06, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) Dec. 18, 2002
Application note Texas Instruments Little Logic Application Report Nov. 01, 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards Jun. 13, 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) May 22, 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices May 10, 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS Mar. 27, 2002
More literature Military Low Voltage Solutions Apr. 04, 2001
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices Dec. 01, 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application note LVC Characterization Information Dec. 01, 1996
Application note Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application note Live Insertion Oct. 01, 1996
User guide Low-Voltage Logic (LVC) Designer's Guide Sep. 01, 1996
Application note Understanding Advanced Bus-Interface Products Design Guide May 01, 1996

Design & development

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Design tools & simulation

SIMULATION MODEL Download
SCEM496.ZIP (56 KB) - IBIS Model

CAD/CAE symbols

Package Pins Download
BGA MICROSTAR JUNIOR (GQL) 56 View options
BGA MICROSTAR JUNIOR (ZQL) 56 View options
SSOP (DL) 48 View options
TSSOP (DGG) 48 View options
TVSOP (DGV) 48 View options

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