810-MHz, JEDEC SSTE32882 compliant 28-bit to 56-bit registered buffer with address-parity test

SN74SSQEA32882

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Product details

Function Memory interface Additive RMS jitter (Typ) (fs) 40 Output frequency (Max) (MHz) 810 Number of outputs 60 Output supply voltage (V) 1.35 Core supply voltage (V) 1.35 Features DDR3 register Operating temperature range (C) 0 to 85 Rating Catalog Output type CMOS Input type CMOS
Function Memory interface Additive RMS jitter (Typ) (fs) 40 Output frequency (Max) (MHz) 810 Number of outputs 60 Output supply voltage (V) 1.35 Core supply voltage (V) 1.35 Features DDR3 register Operating temperature range (C) 0 to 85 Rating Catalog Output type CMOS Input type CMOS
NFBGA (ZAL) 176 108 mm² 13.5 x 8
  • JEDEC SSTE32882 Compliant
  • 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs Support
    Stacked DDR3 RDIMMs
  • CKE Powerdown Mode for Optimized System Power Consumption
  • 1.5V/1.35V Phase Lock Loop Clock Driver for Buffering One
    Differential Clock Pair (CK and CK) and Distributing
    to Four Differential Outputs
  • 1.5V/1.35V CMOS Inputs
  • Checks Parity on Command and Address (CS-Gated) Data Inputs
  • Configurable Driver Strength
  • Uses Internal Feedback Loop
  • APPLICATIONS
    • DDR3 Registered DIMMs up to DDR3-1600
    • DDR3L Registered DIMMs up to DDR3L-1333
    • Single-, Dual- and Quad-Rank RDIMM

  • JEDEC SSTE32882 Compliant
  • 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs Support
    Stacked DDR3 RDIMMs
  • CKE Powerdown Mode for Optimized System Power Consumption
  • 1.5V/1.35V Phase Lock Loop Clock Driver for Buffering One
    Differential Clock Pair (CK and CK) and Distributing
    to Four Differential Outputs
  • 1.5V/1.35V CMOS Inputs
  • Checks Parity on Command and Address (CS-Gated) Data Inputs
  • Configurable Driver Strength
  • Uses Internal Feedback Loop
  • APPLICATIONS
    • DDR3 Registered DIMMs up to DDR3-1600
    • DDR3L Registered DIMMs up to DDR3L-1333
    • Single-, Dual- and Quad-Rank RDIMM

This JEDEC SSTE32882-compliant, 28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 registering clock driver with parity is designed for operation on DDR3 registered DIMMs with VDD of 1.5 V and on DDR3L registered DIMMs with VDD of 1.35 V.

All inputs are 1.5 V and 1.35 V CMOS compatible. All outputs are CMOS drivers optimized to drive DRAM signals on terminated traces in DDR3 RDIMM applications. The clock outputs Yn and Yn and control net outputs DxCKEn, DxCSn and DxODTn can be driven with a different strength and skew to optimize signal integrity, compensate for different loading and equalize signal travel speed.

The SN74SSQEA32882 has two basic modes of operation associated with the Quad Chip Select Enable (QCSEN) input. When the QCSEN input pin is open (or pulled high), the component has two chip select inputs, DCS0 and DCS1, and two copies of each chip select output, QACS0, QACS1, QBCS0 and QBCS1. This is the "QuadCS disabled" mode. When the QCSEN input pin is pulled low, the component has four chip select inputs DCS[3:0], and four chip select outputs, QCS[3:0]. This is the "QuadCS enabled" mode. Through the remainder of this specification, DCS[n:0] will indicate all of the chip select inputs, where n=1 for QuadCS disabled, and n=3 for QuadCS enabled. QxCS[n:0] will indicate all of the chip select outputs.

The device also supports a mode where a single device can be mounted on the back side of a DIMM. If MIRROR=HIGH, Input Bus Termination (IBT) has to stay enabled for all input signals in this case.

The SN74SSQEA32882 operates from a differential clock (CK and CK). Data are registered at the crossing of CK going HIGH, and CK going LOW. This data could be either re-driven to the outputs or it could be used to access device internal control registers.

The input bus data integrity is protected by a parity function. All address and command input signals are added up and the last bit of the sum is compared to the parity signal delivered by the system at the input PAR_IN one clock cycle later. If they do not match the device pulls the open drain output ERROUT LOW. The control signals (DCKE0, DCKE1, DODT0, DODT1, DCS[n:0]) are not part of this computation.

The SN74SSQEA32882 implements different power saving mechanisms to reduce thermal power dissipation and to support system power down states. By disabling unused outputs the power consumption is further reduced.

The package is optimized to support high density DIMMs. By aligning input and output positions towards DIMM finger signal ordering and SDRAM ballout the device de-scrambles the DIMM traces allowing low cross talk design with low interconnect latency.

Edge controlled outputs reduce ringing and improve signal eye opening at the SDRAM inputs.

This JEDEC SSTE32882-compliant, 28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 registering clock driver with parity is designed for operation on DDR3 registered DIMMs with VDD of 1.5 V and on DDR3L registered DIMMs with VDD of 1.35 V.

All inputs are 1.5 V and 1.35 V CMOS compatible. All outputs are CMOS drivers optimized to drive DRAM signals on terminated traces in DDR3 RDIMM applications. The clock outputs Yn and Yn and control net outputs DxCKEn, DxCSn and DxODTn can be driven with a different strength and skew to optimize signal integrity, compensate for different loading and equalize signal travel speed.

The SN74SSQEA32882 has two basic modes of operation associated with the Quad Chip Select Enable (QCSEN) input. When the QCSEN input pin is open (or pulled high), the component has two chip select inputs, DCS0 and DCS1, and two copies of each chip select output, QACS0, QACS1, QBCS0 and QBCS1. This is the "QuadCS disabled" mode. When the QCSEN input pin is pulled low, the component has four chip select inputs DCS[3:0], and four chip select outputs, QCS[3:0]. This is the "QuadCS enabled" mode. Through the remainder of this specification, DCS[n:0] will indicate all of the chip select inputs, where n=1 for QuadCS disabled, and n=3 for QuadCS enabled. QxCS[n:0] will indicate all of the chip select outputs.

The device also supports a mode where a single device can be mounted on the back side of a DIMM. If MIRROR=HIGH, Input Bus Termination (IBT) has to stay enabled for all input signals in this case.

The SN74SSQEA32882 operates from a differential clock (CK and CK). Data are registered at the crossing of CK going HIGH, and CK going LOW. This data could be either re-driven to the outputs or it could be used to access device internal control registers.

The input bus data integrity is protected by a parity function. All address and command input signals are added up and the last bit of the sum is compared to the parity signal delivered by the system at the input PAR_IN one clock cycle later. If they do not match the device pulls the open drain output ERROUT LOW. The control signals (DCKE0, DCKE1, DODT0, DODT1, DCS[n:0]) are not part of this computation.

The SN74SSQEA32882 implements different power saving mechanisms to reduce thermal power dissipation and to support system power down states. By disabling unused outputs the power consumption is further reduced.

The package is optimized to support high density DIMMs. By aligning input and output positions towards DIMM finger signal ordering and SDRAM ballout the device de-scrambles the DIMM traces allowing low cross talk design with low interconnect latency.

Edge controlled outputs reduce ringing and improve signal eye opening at the SDRAM inputs.

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Technical documentation

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Type Title Date
* Data sheet SSQEA32882 DDR3 Register datasheet (Rev. B) 21 Sep 2010
Application note Semiconductor and IC Package Thermal Metrics (Rev. C) 19 Apr 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
Application note Recommendation for Register-Related SPD Settings on DDR3 RDIMM (Rev. B) 26 Jul 2013
Application note Programmable Yn Clock Phase Shift w/SN74SSQEA32882 DDR3 Register 11 Jan 2010
Application note DDR3 Register Input Bus Termination Measurement 16 Nov 2009
Application note CMR Programming for DDR3 Registers 25 Jun 2009
Application note Overview of JEDEC RawCards for DDR3 RDIMM 19 Sep 2008

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