512 x 18 Synchronous FIFO Memory


Product details


We are not able to display this information. Please refer to the product data sheet.

Package | Pins | Size

TQFP (PAG) 64 144 mm² 12 x 12 open-in-new Find other FIFO register


  • 512 × 18-Bit Organization Array (SN74V215)
  • 1024 × 18-Bit Organization Array (SN74V225)
  • 2048 × 18-Bit Organization Array (SN74V235)
  • 4096 × 18-Bit Organization Array (SN74V245)
  • 7.5-ns Read/Write Cycle Time
  • 3.3-V VCC, 5-V Input Tolerant
  • First-Word or Standard Fall-Through Timing
  • Single or Double Register-Buffered Empty and Full Flags
  • Easily Expandable in Depth and Width
  • Asynchronous or Coincident Read and Write Clocks
  • Asynchronous or Synchronous Programmable Almost-Empty and Almost-Full Flags With Default Settings
  • Half-Full Flag Capability
  • Output Enable Puts Output Data Bus in High-Impedance State
  • High-Performance Submicron CMOS Technology
  • Packaged in 64-Pin Thin Quad Flat Package
  • DSP and Microprocessor Interface Control Logic
  • Provide a DSP Glueless Interface to Texas Instruments TMS320™ DSPs

DSP-SYNC and TMS320 are trademarks of Texas Instruments.

open-in-new Find other FIFO register


The SN74V215, SN74V225, SN74V235, and SN74V245 are very high-speed, low-power CMOS clocked first-in first-out (FIFO) memories. They support clock frequencies up to 133 MHz and have read-access times as fast as 5 ns. These DSP-Sync™ FIFO memories feature read and write controls for use in applications such as DSP-to-processor communication, DSP-to-analog front end (AFE) buffering, network, video, and data communications.

These are synchronous FIFOs, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple interface between DSPs, microprocessors, and/or buses controlled by a synchronous interface. An output-enable (OE)\ input controls the 3-state output.

The synchronous FIFOs have two fixed flags, empty flag/output ready (EF\/OR\) and full flag/input ready (FF\/IR\), and two programmable flags, almost-empty (PAE)\ and almost-full (PAF)\. The offset loading of the programmable flags is controlled by a simple state machine, and is initiated by asserting the load pin (LD)\. A half-full flag (HF)\ is available when the FIFO is used in a single-device configuration.

Two timing modes of operation are possible with these devices: first-word fall-through (FWFT) mode and standard mode.

In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. A read enable (REN)\ does not have to be asserted for accessing the first word.

In standard mode, the first word written to an empty FIFO does not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating REN\ and enabling a rising RCLK edge, shifts the word from internal memory to the data output lines.

These devices are depth expandable, using a daisy-chain technique or FWFT mode. The XI\ and XO\ pins are used to expand the FIFOs. In depth-expansion configuration, first load (FL)\ is grounded on the first device and set to high for all other devices in the daisy chain.

The SN74V215, SN74V225, SN74V235, and SN74V245 are characterized for operation from 0°C to 70°C.

open-in-new Find other FIFO register

Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 5
Type Title Date
* Datasheet SN74V215, SN74V225, SN74V235, SN74V245 datasheet (Rev. E) Sep. 13, 2002
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application notes Using TI FIFOs to Interface High-Speed Data Converters With TI TMS320 DSPs Jun. 08, 2001
Application notes Designing With TI SN74V2x5 FIFO Programmable Flags May 14, 2001
Application notes Power-Dissipation Calculations for TI FIFO Products (Rev. A) Mar. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Design tools & simulation

SDFM013.ZIP (4 KB) - IBIS Model

CAD/CAE symbols

Package Pins Download
TQFP (PAG) 64 View options

Ordering & quality

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​


Related videos