Product details


Number of SRC channels 2 Digital audio interface AES/EBU, S/PDIF Dynamic range (dB) 144 Digital supply (up to 5 V) (V) 1.65 - 1.95, 3 - 3.6 THD+N (dB) -140 Control mode SW (SPI), H/W Power supply (V) 1.8, 3.3 Control interface SPI, I2C Audio data format Normal, I2S Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other Sample rate converters

Package | Pins | Size

TQFP (PFB) 48 81 mm² 9 x 9 open-in-new Find other Sample rate converters


  • Two-Channel Asynchronous Sample Rate Converter (SRC)
    • Dynamic Range with –60dB Input (A-Weighted): 144dB typical
    • Total Harmonic Distortion and Noise (THD+N) with Full-Scale Input: –140dB typical
    • Supports Audio Input and Output Data Word Lengths Up to 24 Bits
    • Supports Input and Output Sampling Frequencies Up to 216kHz
    • Automatic Detection of the Input-to-Output Sampling Ratio
    • Wide Input-to-Output Conversion Range:
      16:1 to 1:16 Continuous
    • Excellent Jitter Attenuation Characteristics
    • Digital De-Emphasis Filtering for 32kHz, 44.1kHz, and 48kHz Input Sampling Rates
    • Digital Output Attenuation and Mute Functions
    • Output Word Length Reduction
    • Status Registers and Interrupt Generation for Sampling Ratio and Ready Flags
  • Digital Audio Interface Transmitter (DIT)
    • Supports Sampling Rates Up to 216kHz
    • Includes Differential Line Driver and
      CMOS Buffered Outputs
    • Block-Sized Data Buffers for Both Channel Status and User Data
    • Status Registers and Interrupt Generation for Flag and Error Conditions
  • User-Selectable Serial Host Interface: SPI or Philips I2C™
    • Provides Access to On-Chip Registers and Data Buffers

    U.S. Patent No. 7,262,716

  • Digital Audio Interface Receiver (DIR)
    • PLL Lock Range Includes Sampling Rates from 20kHz to 216kHz
    • Includes Four Differential Input Line Receivers and an Input Multiplexer
    • Bypass Multiplexer Routes Line Receiver Outputs to Line Driver and Buffer Outputs
    • Block-Sized Data Buffers for Both Channel Status and User Data
    • Automatic Detection of Non-PCM Audio Streams (DTS CD/LD and IEC 61937 formats)
    • Audio CD Q-Channel Sub-Code Decoding and Data Buffer
    • Status Registers and Interrupt Generation for Flag and Error Conditions
    • Low Jitter Recovered Clock Output
  • Two Audio Serial Ports (Ports A and B)
    • Synchronous Serial Interface to External Signal Processors, Data Converters, and Logic
    • Slave or Master Mode Operation with Sampling Rates up to 216kHz
    • Supports Left-Justified, Right-Justified, and Philips I2S™ Data Formats
    • Supports Audio Data Word Lengths Up to
      24 Bits
  • Four General-Purpose Digital Outputs
    • Multifunction Programmable Via Control Registers
  • Extensive Power-Down Support
    • Functional Blocks May Be Disabled Individually When Not In Use
  • Operates From +1.8V Core and +3.3V I/O Power Supplies
  • Packages:
    • QFN-40
    • Small TQFP-48 Package, Compatible with the SRC4382 and DIX4192
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The SRC4392 is a highly-integrated CMOS device designed for use in professional and broadcast digital audio systems. The SRC4392 combines a high-performance, two-channel, asynchronous sample rate converter (SRC) with a digital audio interface receiver (DIR) and transmitter (DIT), two audio serial ports, and flexible distribution logic for interconnection of the function block data and clocks.

The DIR and DIT are compatible with the AES3, S/PDIF, IEC 60958, and EIAJ CP-1201 interface standards. The audio serial ports, DIT, and SRC may be operated at sampling rates up to 216kHz. The DIR lock range includes sampling rates from 20kHz to 216kHz.

The SRC4392 is configured using on-chip control registers and data buffers, which are accessed through either a 4-wire serial peripheral interface (SPI) port, or a 2-wire Philips I2C bus interface. Status registers provide access to a variety of flag and error bits, which are derived from the various function blocks. An open drain interrupt output pin is provided, and is supported by flexible interrupt reporting and mask options via control register settings. A master reset input pin is provided for initialization by a host processor or supervisory functions.

The SRC4392 requires a +1.8V core logic supply, in addition to a +3.3V supply for powering portions of the DIR, DIT, and line driver and receiver functions. A separate logic I/O supply supports operation from +1.65V to +3.6V, providing compatibility with low voltage logic interfaces typically found on digital signal processors and programmable logic devices. The SRC4392 is available in a QFN-40 and a lead-free, TQFP-48 package. The TQFN-48 is pin- and register-compatible with the Texas Instruments SRC4382 and DIX4192 products.

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Technical documentation

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Type Title Date
* Data sheet Two-Channel, Asynchronous Sample Rate Converter with Integrated Digital Audio . datasheet (Rev. D) Dec. 18, 2012
User guide SRC4382EVM-PDK and SRC4392EVM-PDK User's Guide (Rev. A) Aug. 25, 2016

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

document-generic User guide

This board supports: TAS2555YZEVMTAS2557EVM and TAS2559EVM.

The Smart Amplifier Speaker Characterization Board, when used in conjunction with a supported TI Smart Amplifier and PurePath Console software, provides users the ability to measure speaker excursion, temperature and other parameters for (...)

  • Easily and quickly characterize speakers
  • Quick connection to TI Smart Amplifier EVMs
  • Microphone included for SPL measurements
  • Laser input for speaker excursion measurements
document-generic User guide

The SRC4392EVM-PDK provides a modular solution for evaluating the function and performance of the SRC4392 device from Texas Instruments. The PDK includes a motherboard (DAIMB) and a daughterboard (SRC4392EVM). These boards are plugged into each other to allow a complete solution for analysis of the (...)

  • Buffered headers support up to four audio and serial interfaces, compatible with I2S™ style or TDM data formats
  • Flexible reference and master clock generation are supported, using either onboard oscillators or external clock sources
  • Onboard linear regulators derive +1.8 V, +3.3 V, and (...)

Design tools & simulation

PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)

Reference designs

Ultrasonic Distance Measurement using the TLV320AIC3268 miniDSP CODEC Reference Design
TIDA-00403 The TIDA-00403 reference design uses off-the-shelf EVMs for ultrasonic distance measurement solutions using algorithms within the TLV320AIC3268 miniDSP. In conjunction with TI’s PurePath Studio design suite, a robust and user configurable ultrasonic distance measurement system can be designed (...)
document-generic Schematic document-generic User guide
High Fidelity Audio Headphone Playback Reference Design for Portable and Smartphone Applications
TIDA-00385 Since the use of high fidelity headphones is a growing trend for portable audio playback, higher performance DAC and Headphone Amplifiers are demanded. This system converts digital audio from USB, SPDIF, or optical sources into analog using PCM5242 audio DAC. A high performance TPA6120A2 headphone (...)
document-generic Schematic document-generic User guide

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TQFP (PFB) 48 View options

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