Product details

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PDIP (P) 8 93 mm² 9.81 x 9.43 SOIC (D) 8 19 mm² 4.9 x 3.9 SOIC (D) 8 19 mm² 3.91 x 4.9
  • Very Low Power Consumption
    1 mW Typ at VDD = 5 V
  • Capable of Operation in Astable Mode
  • CMOS Output Capable of Swinging Rail
    to Rail
  • High Output-Current Capability
    Sink 100 mA Typ
    Source 10 mA Typ
  • Output Fully Compatible With CMOS, TTL, and MOS
  • Low Supply Current Reduces Spikes During Output Transitions
  • Single-Supply Operation From 1 V to 15 V
  • Functionally Interchangeable With the NE555; Has Same Pinout
  • ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015.2
  • Very Low Power Consumption
    1 mW Typ at VDD = 5 V
  • Capable of Operation in Astable Mode
  • CMOS Output Capable of Swinging Rail
    to Rail
  • High Output-Current Capability
    Sink 100 mA Typ
    Source 10 mA Typ
  • Output Fully Compatible With CMOS, TTL, and MOS
  • Low Supply Current Reduces Spikes During Output Transitions
  • Single-Supply Operation From 1 V to 15 V
  • Functionally Interchangeable With the NE555; Has Same Pinout
  • ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015.2

The TLC551 is a monolithic timing circuit fabricated using the TI LinCMOSTM

process. The

timer is fully compatible with CMOS, TTL, and MOS logic and operates at frequencies up to 2 MHz. Compared to the NE555 timer, this device uses smaller timing capacitors because of its high input impedance. As a result, more accurate time delays and oscillations are possible. Power consumption is low across the full range of power supply voltage.

Like the NE555, the TLC551 has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs and can be used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between DISCH and GND. All unused inputs should be tied to an appropriate logic level to prevent false triggering.

While the CMOS output is capable of sinking over 100 mA and sourcing over 10 mA, the TLC551 exhibits greatly reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling capacitors required by the NE555.

The TLC551C is characterized for operation from 0°C to 7

The TLC551 is a monolithic timing circuit fabricated using the TI LinCMOSTM

process. The

timer is fully compatible with CMOS, TTL, and MOS logic and operates at frequencies up to 2 MHz. Compared to the NE555 timer, this device uses smaller timing capacitors because of its high input impedance. As a result, more accurate time delays and oscillations are possible. Power consumption is low across the full range of power supply voltage.

Like the NE555, the TLC551 has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs and can be used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between DISCH and GND. All unused inputs should be tied to an appropriate logic level to prevent false triggering.

While the CMOS output is capable of sinking over 100 mA and sourcing over 10 mA, the TLC551 exhibits greatly reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling capacitors required by the NE555.

The TLC551C is characterized for operation from 0°C to 7

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Type Title Date
* Data sheet LinCMOS Timers datasheet (Rev. B) 25 Sep 1997

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Simulation model

TLC551 TINA-TI Mono Reference Design

SLAM125.TSC (155 KB) - TINA-TI Reference Design
Simulation model

TLC551 TINA-TI Astable Reference Design

SLAM126.TSC (96 KB) - TINA-TI Reference Design
Simulation model

TLC551 PSpice Model

SLAM127.ZIP (102 KB) - PSpice Model
Simulation model

TLC551 TINA-TI Spice Model

SLAM128.ZIP (9 KB) - TINA-TI Spice Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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PDIP (P) 8 View options
SOIC (D) 8 View options

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