Product details

Function General-purpose timer Iq (typ) (mA) 0.34 Rating Catalog Operating temperature range (°C) 0 to 70 Supply voltage (max) (V) 18 Supply voltage (min) (V) 1
Function General-purpose timer Iq (typ) (mA) 0.34 Rating Catalog Operating temperature range (°C) 0 to 70 Supply voltage (max) (V) 18 Supply voltage (min) (V) 1
PDIP (N) 14 181.42 mm² 19.3 x 9.4 SOIC (D) 14 51.9 mm² 8.65 x 6
  • Very Low Power Consumption . . . 2 mW Typ at VDD = 5 V
  • Capable of Operation in Astable Mode
  • CMOS Output Capable of Swinging Rail to Rail
  • High Output-Current Capability
    Sink 100 mA Typ
    Source 10 mA Typ
  • Output Fully Compatible With CMOS, TTL, and MOS
  • Low Supply Current Reduces Spikes During Output Transitions
  • High-Impedance Inputs . . . 1012 Typ
  • Single-Supply Operation From 1 V to 18 V
  • Functionally Interchangeable With the NE556; Has Same Pinout

  • Very Low Power Consumption . . . 2 mW Typ at VDD = 5 V
  • Capable of Operation in Astable Mode
  • CMOS Output Capable of Swinging Rail to Rail
  • High Output-Current Capability
    Sink 100 mA Typ
    Source 10 mA Typ
  • Output Fully Compatible With CMOS, TTL, and MOS
  • Low Supply Current Reduces Spikes During Output Transitions
  • High-Impedance Inputs . . . 1012 Typ
  • Single-Supply Operation From 1 V to 18 V
  • Functionally Interchangeable With the NE556; Has Same Pinout

The TLC552 is a dual monolithic timing circuit fabricated using TI LinCMOSTM process, which provides full compatibility with CMOS, TTL, and MOS logic and operation at frequencies up to 2 MHz. Accurate time delays and oscillations are possible with smaller, less-expensive timing capacitors than the NE555 because of the high input impedance. Power consumption is low across the full range of power supply voltages.

Like the NE556, the TLC552 has a trigger level approximately one-third of the supply voltage and a threshold level approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set and the output goes high. If the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is reset and the output is low. The reset input can override all other inputs and can be used to initiate a new timing cycle. If the reset input is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge terminal and ground.

While the CMOS output is capable of sinking over 100 mA and sourcing over 10 mA, the TLC552 exhibits greatly reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling capacitors required by the NE556.

These devices have internal electrostatic discharge (ESD) protection circuits that will prevent catastrophic failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3105.2. However, care should be exercised in handling these devices as exposure to ESD may result in a degradation of the device parametric performance.

All unused inputs should be tied to an appropriate logic level to prevent false triggering.

The TLC552C is characterized for operation from 0°C to 70°C.

The TLC552 is a dual monolithic timing circuit fabricated using TI LinCMOSTM process, which provides full compatibility with CMOS, TTL, and MOS logic and operation at frequencies up to 2 MHz. Accurate time delays and oscillations are possible with smaller, less-expensive timing capacitors than the NE555 because of the high input impedance. Power consumption is low across the full range of power supply voltages.

Like the NE556, the TLC552 has a trigger level approximately one-third of the supply voltage and a threshold level approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set and the output goes high. If the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is reset and the output is low. The reset input can override all other inputs and can be used to initiate a new timing cycle. If the reset input is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge terminal and ground.

While the CMOS output is capable of sinking over 100 mA and sourcing over 10 mA, the TLC552 exhibits greatly reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling capacitors required by the NE556.

These devices have internal electrostatic discharge (ESD) protection circuits that will prevent catastrophic failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3105.2. However, care should be exercised in handling these devices as exposure to ESD may result in a degradation of the device parametric performance.

All unused inputs should be tied to an appropriate logic level to prevent false triggering.

The TLC552C is characterized for operation from 0°C to 70°C.

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* Data sheet Dual LinCMOS Timer datasheet 01 May 1988

Design & development

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Simulation model

TLC551 and TLC552 PSpice Model (Rev. A)

SLAM127A.ZIP (29 KB) - PSpice Model
Simulation model

TLC552 TINA-TI Astable Reference Design (Rev. B)

SLTM002B.TSC (626 KB) - TINA-TI Reference Design
Simulation model

TLC552 TINA-TI Mono Reference Design (Rev. B)

SLTM003B.TSC (156 KB) - TINA-TI Reference Design
Simulation model

TLC552 TINA-TI Spice Model (Rev. B)

SLTM001B.ZIP (9 KB) - TINA-TI Spice Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Package Pins CAD symbols, footprints & 3D models
PDIP (N) 14 Ultra Librarian
SOIC (D) 14 Ultra Librarian

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