Product details

Iq (Typ) (uA) 130 Rating Catalog Operating temperature range (C) -40 to 85, -55 to 125, 0 to 70 Supply voltage (Max) (V) 15 Supply voltage (Min) (V) 2
Iq (Typ) (uA) 130 Rating Catalog Operating temperature range (C) -40 to 85, -55 to 125, 0 to 70 Supply voltage (Max) (V) 15 Supply voltage (Min) (V) 2
PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6
  • Very Low Power Consumption...2 mW Typ at VDD = 5 V
  • Capable of Operation in Astable Mode
  • CMOS Output Capable of Swinging Rail to Rail
  • High Output-Current Capability
    Sink 100 mA Typ
    Source 10 mA Typ
  • Output Fully Compatible With CMOS, TTL, and MOS
  • Low Supply Current Reduces Spikes During Output Transitions
  • Single-Supply Operation From 2 V to 15 V
  • Functionally interchangeable With the NE556; Has Same Pinout

LinCMOS is a trademark of Texas Instruments Incorporated.

  • Very Low Power Consumption...2 mW Typ at VDD = 5 V
  • Capable of Operation in Astable Mode
  • CMOS Output Capable of Swinging Rail to Rail
  • High Output-Current Capability
    Sink 100 mA Typ
    Source 10 mA Typ
  • Output Fully Compatible With CMOS, TTL, and MOS
  • Low Supply Current Reduces Spikes During Output Transitions
  • Single-Supply Operation From 2 V to 15 V
  • Functionally interchangeable With the NE556; Has Same Pinout

LinCMOS is a trademark of Texas Instruments Incorporated.

The TLC556 series are monolithic timing circuits fabricated using the TI LinCMOSTM process, which provides full compatibility with CMOS, TTL, and MOS logic and operates at frequencies up to 2MHz. Accurate time delays and oscillations are possible with smaller, less-expensive timing capacitors than the NE556 because of the high input impedance. Power consumption is low across the full range of power supply voltages.

Like the NE556, the TLC556 has a trigger level approximately one-third of the supply voltage and

a threshold level approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set and the output goes high. If the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is reset and the output is low. The reset input can override all other inputs and can be used to initiate a new timing cycle. If the reset input is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge terminal and ground.

While the CMOS output is capable of sinking over 100 mA and sourcing over 10 mA, the TLC556 exhibits greatly reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling capacitors required by the NE556.

These devices have internal electrostatic-discharge (ESD) protection circuits that prevent catastrophic failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015. However, care should be exercised in handling these devices, as exposure to ESD may result in degradation of the device parametric performance.

All unused inputs should be tied to an appropriate logic level to prevent false triggering.

The TLC556C is characterized for operation from 0°C to 70°C. The TLC556I is characterized for operation from -40°C to 85°C. The TLC556M is characterized for operation over the full military temperature range of -55°C to 125°C

The TLC556 series are monolithic timing circuits fabricated using the TI LinCMOSTM process, which provides full compatibility with CMOS, TTL, and MOS logic and operates at frequencies up to 2MHz. Accurate time delays and oscillations are possible with smaller, less-expensive timing capacitors than the NE556 because of the high input impedance. Power consumption is low across the full range of power supply voltages.

Like the NE556, the TLC556 has a trigger level approximately one-third of the supply voltage and

a threshold level approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set and the output goes high. If the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is reset and the output is low. The reset input can override all other inputs and can be used to initiate a new timing cycle. If the reset input is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge terminal and ground.

While the CMOS output is capable of sinking over 100 mA and sourcing over 10 mA, the TLC556 exhibits greatly reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling capacitors required by the NE556.

These devices have internal electrostatic-discharge (ESD) protection circuits that prevent catastrophic failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015. However, care should be exercised in handling these devices, as exposure to ESD may result in degradation of the device parametric performance.

All unused inputs should be tied to an appropriate logic level to prevent false triggering.

The TLC556C is characterized for operation from 0°C to 70°C. The TLC556I is characterized for operation from -40°C to 85°C. The TLC556M is characterized for operation over the full military temperature range of -55°C to 125°C

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* Data sheet Dual LinCMOS Timers datasheet (Rev. B) 25 Sep 1997

Design & development

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Simulation model

TLC556 TINA-TI Spice Model (Rev. A) TLC556 TINA-TI Spice Model (Rev. A)

Simulation model

TLC556 TINA-TI Mono Reference Design TLC556 TINA-TI Mono Reference Design

Simulation model

TLC556 PSpice Model TLC556 PSpice Model

Simulation model

TLC556 TINA-TI Astable Reference Design TLC556 TINA-TI Astable Reference Design

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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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PDIP (N) 14 View options
SOIC (D) 14 View options

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