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TS3DS26227

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3.3-V, 2:1 (SPDT), 2-channel differential signal switch with input logic translation

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Data sheet

TS3DS26227

LAST TIME BUY
Data sheet Order now

Product details

Protocols MIPI Configuration 2:1 SPDT Number of channels 2 Bandwidth (MHz) 800 Supply voltage (max) (V) 3.6 Supply voltage (min) (V) 2.3 Ron (typ) (mΩ) 3500 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 3.6 Supply current (typ) (µA) 0.1 ESD HBM (typ) (kV) 4 Operating temperature range (°C) -40 to 85 Crosstalk (dB) -39 ESD CDM (kV) 1 Input/output continuous current (max) (mA) 64 COFF (typ) (pF) 3.5 CON (typ) (pF) 10.5 Off isolation (typ) (dB) -40 OFF-state leakage current (max) (µA) 0.015 Ron (max) (mΩ) 7000 Ron channel match (max) (Ω) 0.2 RON flatness (typ) (Ω) 3 Turnoff time (disable) (max) (ns) 5 Turnon time (enable) (max) (ns) 13 VIH (min) (V) VIO * .65 VIL (max) (V) VIO * .35 Rating Catalog
Protocols MIPI Configuration 2:1 SPDT Number of channels 2 Bandwidth (MHz) 800 Supply voltage (max) (V) 3.6 Supply voltage (min) (V) 2.3 Ron (typ) (mΩ) 3500 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 3.6 Supply current (typ) (µA) 0.1 ESD HBM (typ) (kV) 4 Operating temperature range (°C) -40 to 85 Crosstalk (dB) -39 ESD CDM (kV) 1 Input/output continuous current (max) (mA) 64 COFF (typ) (pF) 3.5 CON (typ) (pF) 10.5 Off isolation (typ) (dB) -40 OFF-state leakage current (max) (µA) 0.015 Ron (max) (mΩ) 7000 Ron channel match (max) (Ω) 0.2 RON flatness (typ) (Ω) 3 Turnoff time (disable) (max) (ns) 5 Turnon time (enable) (max) (ns) 13 VIH (min) (V) VIO * .65 VIL (max) (V) VIO * .35 Rating Catalog
DSBGA (YZT) 12 3.9375 mm² 2.25 x 1.75
  • High-Bandwidth Data Paths – Up to 800 MHz
  • Specified Break-Before-Make Switching
  • Control Inputs Reference to VIO
  • Low Charge Injection
  • Excellent ON-State Resistance Matching
  • Low Total Harmonic Distortion (THD)
  • 2.3-V to 3.6-V Power Supply (V+)
  • 1.65-V to 1.95-V Logic Supply (VIO)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 4000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
    • 200-V Machine Model (A115-A)
  • High-Bandwidth Data Paths – Up to 800 MHz
  • Specified Break-Before-Make Switching
  • Control Inputs Reference to VIO
  • Low Charge Injection
  • Excellent ON-State Resistance Matching
  • Low Total Harmonic Distortion (THD)
  • 2.3-V to 3.6-V Power Supply (V+)
  • 1.65-V to 1.95-V Logic Supply (VIO)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 4000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
    • 200-V Machine Model (A115-A)

The TS3DS26227 is a dual single-pole double-throw (SPDT) analog switch that is designed to operate from
2.3 V to 3.6 V. The device offers high-bandwidth data paths, and a break-before-make feature to prevent signal distortion during the transferring of a signal from one path to another. The device has excellent total harmonic distortion (THD) performance and consumes very low power. These features make this device suitable for portable applications.

The TS3DS26227 has a separate logic supply pin (VIO) that operates from 1.65 V to 1.95 V. VIO powers the control circuitry, which allows the TS3DS26227 to be controlled by 1.8-V signals.

The TS3DS26227 is a dual single-pole double-throw (SPDT) analog switch that is designed to operate from
2.3 V to 3.6 V. The device offers high-bandwidth data paths, and a break-before-make feature to prevent signal distortion during the transferring of a signal from one path to another. The device has excellent total harmonic distortion (THD) performance and consumes very low power. These features make this device suitable for portable applications.

The TS3DS26227 has a separate logic supply pin (VIO) that operates from 1.65 V to 1.95 V. VIO powers the control circuitry, which allows the TS3DS26227 to be controlled by 1.8-V signals.
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* Data sheet High-Bandwidth Dual SPDT Differential Signal Switch With Input Logic Translation datasheet (Rev. B) 20 Nov 2010

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