Product details

Technology family TXS Applications SPIO Bits (#) 4 Data rate (max) (Mbps) 24 High input voltage (min) (V) 1.45 High input voltage (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 IOH (max) (mA) 0 IOL (max) (mA) 0 Supply current (max) (µA) 10 Features Edge rate accelerator, Output enable, Vcc isolation Input type Transmission Gate Output type 3-State, Transmission Gate Rating Catalog Operating temperature range (°C) -40 to 125
Technology family TXS Applications SPIO Bits (#) 4 Data rate (max) (Mbps) 24 High input voltage (min) (V) 1.45 High input voltage (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 IOH (max) (mA) 0 IOL (max) (mA) 0 Supply current (max) (µA) 10 Features Edge rate accelerator, Output enable, Vcc isolation Input type Transmission Gate Output type 3-State, Transmission Gate Rating Catalog Operating temperature range (°C) -40 to 125
DSBGA (YZT) 12 3.9375 mm² 2.25 x 1.75 NFBGA (NMN) 12 5 mm² 2 x 2.5 SOIC (D) 14 51.9 mm² 8.65 x 6 TSSOP (PW) 14 32 mm² 5 x 6.4 UQFN (RUT) 12 3.4 mm² 2 x 1.7 VQFN (RGY) 14 12.25 mm² 3.5 x 3.5 WQFN (BQA) 14 7.5 mm² 3 x 2.5
  • No direction-control signal needed
  • Maximum data rates:
    • 24Mbps (push pull)
    • 2Mbps (open drain)
  • Available in the Texas Instruments NanoFree™ package
  • 1.65 V to 3.6 V on A port and 2.3 V to 5.5 V on B port (V CCA ≤ V CCB)
  • No power-supply sequencing required – V CCA or V CCB can be ramped first
  • Latch-up performance exceeds 100 mA per JESD 78, class II
  • ESD protection exceeds JESD 22:
    • A port:
      • 2000-V Human-Body Model (A114-B)
      • 200-V Machine Model (A115-A)
      • 1000-V Charged-Device Model (C101)
    • B port:
      • 15-kV Human-Body Model (A114-B)
      • 200-V Machine Model (A115-A)
      • 1000-V Charged-Device Model (C101)
  • IEC 61000-4-2 ESD (B port):
    • ±8-kV contact discharge
    • ±10-kV air-gap discharge
  • No direction-control signal needed
  • Maximum data rates:
    • 24Mbps (push pull)
    • 2Mbps (open drain)
  • Available in the Texas Instruments NanoFree™ package
  • 1.65 V to 3.6 V on A port and 2.3 V to 5.5 V on B port (V CCA ≤ V CCB)
  • No power-supply sequencing required – V CCA or V CCB can be ramped first
  • Latch-up performance exceeds 100 mA per JESD 78, class II
  • ESD protection exceeds JESD 22:
    • A port:
      • 2000-V Human-Body Model (A114-B)
      • 200-V Machine Model (A115-A)
      • 1000-V Charged-Device Model (C101)
    • B port:
      • 15-kV Human-Body Model (A114-B)
      • 200-V Machine Model (A115-A)
      • 1000-V Charged-Device Model (C101)
  • IEC 61000-4-2 ESD (B port):
    • ±8-kV contact discharge
    • ±10-kV air-gap discharge

This 4-bit non-inverting translator uses two separate configurable power-supply rails. The A port is designed to track V CCA. V CCA accepts any supply voltage from 1.65 V to 3.6 V. V CCA must be less than or equal to V CCB. The B port is designed to track V CCB. V CCB accepts any supply voltage from 2.3 V to 5.5 V. This allows for low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.

When the output-enable (OE) input is low, all outputs are placed in the high-impedance state.

The TXS0104E is designed so that the OE input circuit is supplied by V CCA.

For the high-impedance state during power up or power down, tie OE to GND through a pull-down resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

This 4-bit non-inverting translator uses two separate configurable power-supply rails. The A port is designed to track V CCA. V CCA accepts any supply voltage from 1.65 V to 3.6 V. V CCA must be less than or equal to V CCB. The B port is designed to track V CCB. V CCB accepts any supply voltage from 2.3 V to 5.5 V. This allows for low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.

When the output-enable (OE) input is low, all outputs are placed in the high-impedance state.

The TXS0104E is designed so that the OE input circuit is supplied by V CCA.

For the high-impedance state during power up or power down, tie OE to GND through a pull-down resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

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Technical documentation

Design & development

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User guide: PDF | HTML
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Evaluation board

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User guide: PDF | HTML
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Design guide: PDF
Schematic: PDF
Package Pins Download
DSBGA (YZT) 12 View options
NFBGA (NMN) 12 View options
SOIC (D) 14 View options
TSSOP (PW) 14 View options
UQFN (RUT) 12 View options
VQFN (RGY) 14 View options
WQFN (BQA) 14 View options

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