Product details

Technology Family TXS Applications SPIO Bits (#) 4 High input voltage (Min) (Vih) 1.45 High input voltage (Max) (Vih) 5.5 Vout (Min) (V) 1.65 Vout (Max) (V) 5.5 IOH (Max) (mA) 0 IOL (Max) (mA) 0 Rating Catalog
Technology Family TXS Applications SPIO Bits (#) 4 High input voltage (Min) (Vih) 1.45 High input voltage (Max) (Vih) 5.5 Vout (Min) (V) 1.65 Vout (Max) (V) 5.5 IOH (Max) (mA) 0 IOL (Max) (mA) 0 Rating Catalog
DSBGA (YZT) 12 0 mm² 1.4 x 1.9 NFBGA (NMN) 12 5 mm² 2 x 2.5 SOIC (D) 14 52 mm² 8.65 x 6 TSSOP (PW) 14 32 mm² 5 x 6.4 VQFN (RGY) 14 12 mm² 3.5 x 3.5
  • No Direction-Control Signal Needed
  • Max Data Rates
    • 24 Mbps (Push Pull)
    • 2 Mbps (Open Drain)
  • Available in the Texas Instruments NanoFree™ Package
  • 1.65 V to 3.6 V on A port and 2.3 V to 5.5 V on B port (VCCA ≤ VCCB)
  • No Power-Supply Sequencing Required – VCCA or VCCB Can Be Ramped First
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • A Port
      • 2000-V Human-Body Model (A114-B)
      • 200-V Machine Model (A115-A)
      • 1000-V Charged-Device Model (C101)
    • B Port
      • 15-kV Human-Body Model (A114-B)
      • 200-V Machine Model (A115-A)
      • 1000-V Charged-Device Model (C101)
  • IEC 61000-4-2 ESD (B Port)
    • ±8-kV Contact Discharge
    • ±10-kV Air-Gap Discharge
  • No Direction-Control Signal Needed
  • Max Data Rates
    • 24 Mbps (Push Pull)
    • 2 Mbps (Open Drain)
  • Available in the Texas Instruments NanoFree™ Package
  • 1.65 V to 3.6 V on A port and 2.3 V to 5.5 V on B port (VCCA ≤ VCCB)
  • No Power-Supply Sequencing Required – VCCA or VCCB Can Be Ramped First
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • A Port
      • 2000-V Human-Body Model (A114-B)
      • 200-V Machine Model (A115-A)
      • 1000-V Charged-Device Model (C101)
    • B Port
      • 15-kV Human-Body Model (A114-B)
      • 200-V Machine Model (A115-A)
      • 1000-V Charged-Device Model (C101)
  • IEC 61000-4-2 ESD (B Port)
    • ±8-kV Contact Discharge
    • ±10-kV Air-Gap Discharge

This 4-bit non-inverting translator uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65 V to 3.6 V. VCCA must be less than or equal to VCCB. The B port is designed to track VCCB. VCCB accepts any supply voltage from 2.3 V to 5.5 V. This allows for low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.

When the output-enable (OE) input is low, all outputs are placed in the high-impedance state.

The TXS0104E is designed so that the OE input circuit is supplied by VCCA.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

This 4-bit non-inverting translator uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65 V to 3.6 V. VCCA must be less than or equal to VCCB. The B port is designed to track VCCB. VCCB accepts any supply voltage from 2.3 V to 5.5 V. This allows for low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.

When the output-enable (OE) input is low, all outputs are placed in the high-impedance state.

The TXS0104E is designed so that the OE input circuit is supplied by VCCA.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

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Technical documentation

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Type Title Date
* Data sheet TXS0104E 4-Bit Bidirectional Voltage-Level Translator for Open-Drain Push-Pull A datasheet (Rev. I) 09 Oct 2020
EVM User's guide TXS-EVM User's Guide (Rev. B) PDF | HTML 08 Jun 2021
Selection guide Voltage Translation Buying Guide (Rev. A) 15 Apr 2021
Application note Effects of pullup and pulldown resistors on TXS and TXB devices (Rev. A) 28 Mar 2018
Application note A Guide to Voltage Translation With TXS-Type Translators 29 Jun 2010

Design & development

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Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, DYY, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.

Not available on TI.com
Evaluation board

14-24-NL-LOGIC-EVM — Generic 14 through 24 pin non-leaded package evaluation module

Flexible EVM designed to support any logic or translation device that has a BQA, BQB, RGY (14-24 pin), RSV, RJW, or RHL package.
Not available on TI.com
Driver or library

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Reference designs

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Package Pins Download
DSBGA (YZT) 12 View options
NFBGA (NMN) 12 View options
SOIC (D) 14 View options
TSSOP (PW) 14 View options
VQFN (RGY) 14 View options

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