Product details

Technology family AVC Applications GPIO, JTAG, RGMII, SPI, UART Bits (#) 6 High input voltage (min) (V) 1.08 High input voltage (max) (V) 3.6 Vout (min) (V) 1.65 Vout (max) (V) 3.6 Data rate (max) (MBps) 250 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 16 Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff), Vcc isolation Input type Standard CMOS Output type 3-State, Balanced CMOS, Push-Pull Rating Automotive Operating temperature range (°C) -40 to 125
Technology family AVC Applications GPIO, JTAG, RGMII, SPI, UART Bits (#) 6 High input voltage (min) (V) 1.08 High input voltage (max) (V) 3.6 Vout (min) (V) 1.65 Vout (max) (V) 3.6 Data rate (max) (MBps) 250 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 16 Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff), Vcc isolation Input type Standard CMOS Output type 3-State, Balanced CMOS, Push-Pull Rating Automotive Operating temperature range (°C) -40 to 125
WQFN (BQB) 16 8.75 mm² 3.5 x 2.5
  • AEC-Q100 qualified for automotive applications
  • Integrated damping output resistor

  • Fixed direction voltage level shifter and buffer for general and skew sensitive applications
  • Meets RGMII 2.0 standard timing specifications:
    • < 750 ps rise and fall time
    • < 400 ps channel to channel skew
    • < ± 5% duty cycle distortion
  • Fully configurable symmetric dual-rail design allows each port to operate from 1.65 V to 3.6 V
  • Supports up to 320-Mbps for 1.65 V to 3.6 V
    • 250-Mbps maximum to meet RGMII timing specs
  • High drive strength (up to 12 mA at 3.6 V)
  • Low power consumption:
    • 10-µA maximum (25°C)
    • 20-µA maximum (–40°C to 125°C)
  • Operating temperature from –40°C to +125°C
  • Latch-up performance exceeds 100 mA per JESD 78, Class II
  • ESD protection exceeds JESD 22:
    • 2000-V Human-Body Model
    • 1000-V Charged-Device Model
  • AEC-Q100 qualified for automotive applications
  • Integrated damping output resistor

  • Fixed direction voltage level shifter and buffer for general and skew sensitive applications
  • Meets RGMII 2.0 standard timing specifications:
    • < 750 ps rise and fall time
    • < 400 ps channel to channel skew
    • < ± 5% duty cycle distortion
  • Fully configurable symmetric dual-rail design allows each port to operate from 1.65 V to 3.6 V
  • Supports up to 320-Mbps for 1.65 V to 3.6 V
    • 250-Mbps maximum to meet RGMII timing specs
  • High drive strength (up to 12 mA at 3.6 V)
  • Low power consumption:
    • 10-µA maximum (25°C)
    • 20-µA maximum (–40°C to 125°C)
  • Operating temperature from –40°C to +125°C
  • Latch-up performance exceeds 100 mA per JESD 78, Class II
  • ESD protection exceeds JESD 22:
    • 2000-V Human-Body Model
    • 1000-V Charged-Device Model

The TXV0106-Q1 is a 6-bit, dual-supply fixed-direction low-skew, low jitter voltage translation device. This device can be used for buffering or redriving and voltage translation on transmitting skew sensitive interfaces, such as RGMII signals between MAC and PHY. Ax pins and enable pin ( OE) are referenced to V CCA logic levels, and Bx pins are referenced to V CCB logic levels. This device has an improved channel-to-channel skew, duty cycle distortion and symmetric rise or fall timing for applications requiring strict timing conditions.

For the high-impedance state during power up or power down, tie OE to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. See Device Functional Modes for a summary of the operation of the control logic.

The TXV0106-Q1 is a 6-bit, dual-supply fixed-direction low-skew, low jitter voltage translation device. This device can be used for buffering or redriving and voltage translation on transmitting skew sensitive interfaces, such as RGMII signals between MAC and PHY. Ax pins and enable pin ( OE) are referenced to V CCA logic levels, and Bx pins are referenced to V CCB logic levels. This device has an improved channel-to-channel skew, duty cycle distortion and symmetric rise or fall timing for applications requiring strict timing conditions.

For the high-impedance state during power up or power down, tie OE to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. See Device Functional Modes for a summary of the operation of the control logic.

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Technical documentation

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* Data sheet TXV0106-Q1 Automotive 6-Bit Fix Direction Low-Skew,Low-Jitter Voltage Translator or Buffer datasheet PDF | HTML 26 Jul 2023
Application note Enabling Industrial and Automotive Ethernet RGMII Interfaces with Voltage Transl PDF | HTML 02 Aug 2023

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-NL-LOGIC-EVM — Generic 14 through 24 pin non-leaded package evaluation module

Flexible EVM designed to support any logic or translation device that has a BQA, BQB, RGY (14-24 pin), RSV, RJW, or RHL package.
User guide: PDF | HTML
Not available on TI.com
Package Pins Download
WQFN (BQB) 16 View options

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