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Ähnliche Funktionalität wie der verglichene Baustein.
ADC3910D065 AKTIV 10-Bit-, 2-Kanal-, 65-MSPS-A/D-Wandler mit einzelner Taktzyklus-Latenz, bis zu 16x Dezimation, digit Lower power and smaller package size

Produktdetails

Sample rate (max) (Msps) 65 Resolution (Bits) 10 Number of input channels 2 Interface type Parallel CMOS, TTL Analog input BW (MHz) 250 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 370 Architecture Pipeline SNR (dB) 61 ENOB (Bits) 9.8 SFDR (dB) 86 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 65 Resolution (Bits) 10 Number of input channels 2 Interface type Parallel CMOS, TTL Analog input BW (MHz) 250 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 370 Architecture Pipeline SNR (dB) 61 ENOB (Bits) 9.8 SFDR (dB) 86 Operating temperature range (°C) -40 to 85 Input buffer No
TQFP (PAG) 64 144 mm² (12 mm × 12 mm)
  • Single +3.3V Supply Operation
  • Internal Sample-and-Hold
  • Internal Reference
  • Outputs 2.4V to 3.6V Compatible
  • Power Down Mode
  • Duty Cycle Stabilizer
  • Multiplexed Output Mode

Key Specifications

  • Resolution 10 Bits
  • DNL ±0.16 LSB (typ)
  • SNR (fIN = 10 MHz) 61 dB (typ)
  • SFDR (fIN = 10 MHz) 85 dB (typ)
  • Data Latency 7 Clock Cycles
  • Power Consumption
    • Operating 370 mW (typ)
    • Power Down Mode 36 mW (typ)

All trademarks are the property of their respective owners.

  • Single +3.3V Supply Operation
  • Internal Sample-and-Hold
  • Internal Reference
  • Outputs 2.4V to 3.6V Compatible
  • Power Down Mode
  • Duty Cycle Stabilizer
  • Multiplexed Output Mode

Key Specifications

  • Resolution 10 Bits
  • DNL ±0.16 LSB (typ)
  • SNR (fIN = 10 MHz) 61 dB (typ)
  • SFDR (fIN = 10 MHz) 85 dB (typ)
  • Data Latency 7 Clock Cycles
  • Power Consumption
    • Operating 370 mW (typ)
    • Power Down Mode 36 mW (typ)

All trademarks are the property of their respective owners.

The ADC10DL065 is a dual, low power monolithic CMOS analog-to-digital converter capable of converting analog input signals into 10-bit digital words at 65 Megasamples per second (MSPS). This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption while providing excellent dynamic performance and a 250 MHz Full Power Bandwidth. Operating on a single +3.3V power supply, the ADC10DL065 achieves 9.8 effective bits at nyquist and consumes just 370 mW at 65 MSPS, including the reference current. The Power Down feature reduces power consumption to 36 mW.

The differential inputs provide a full scale differential input swing equal to 2 times VREF with the possibility of a single-ended input. Full use of the differential input is recommended for optimum performance. The digital outputs from the two ADC's are available on a single multiplexed 10-bit bus or on separate buses. Duty cycle stabilization and output data format are selectable using a quad state function pin. The output data can be set for offset binary or two's complement.

To ease interfacing to lower voltage systems, the digital output driver power pins of the ADC10DL065 can be connected to a separate supply voltage in the range of 2.4V to the analog supply voltage. This device is available in the 64-lead TQFP package and will operate over the industrial temperature range of −40°C to +85°C. An evaluation board is available to ease the evaluation process.

The ADC10DL065 is a dual, low power monolithic CMOS analog-to-digital converter capable of converting analog input signals into 10-bit digital words at 65 Megasamples per second (MSPS). This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption while providing excellent dynamic performance and a 250 MHz Full Power Bandwidth. Operating on a single +3.3V power supply, the ADC10DL065 achieves 9.8 effective bits at nyquist and consumes just 370 mW at 65 MSPS, including the reference current. The Power Down feature reduces power consumption to 36 mW.

The differential inputs provide a full scale differential input swing equal to 2 times VREF with the possibility of a single-ended input. Full use of the differential input is recommended for optimum performance. The digital outputs from the two ADC's are available on a single multiplexed 10-bit bus or on separate buses. Duty cycle stabilization and output data format are selectable using a quad state function pin. The output data can be set for offset binary or two's complement.

To ease interfacing to lower voltage systems, the digital output driver power pins of the ADC10DL065 can be connected to a separate supply voltage in the range of 2.4V to the analog supply voltage. This device is available in the 64-lead TQFP package and will operate over the industrial temperature range of −40°C to +85°C. An evaluation board is available to ease the evaluation process.

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Technische Dokumentation

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Top-Dokumentation Typ Titel Format-Optionen Neueste englische Version herunterladen Datum
* Datenblatt ADC10DL065 Dual 10-Bit, 65 MSPS, 3.3V, 370mW A/D Converter datasheet (Rev. B) 18.04.2013
Benutzerhandbuch ADC10DL065/ADC12DL040/ADC12DL065 Instruction Manual 21.02.2012
Anwendungshinweis Understanding High-Speed Signals, Clocks, and Data Capture 18.10.2005

Design und Entwicklung

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Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
TQFP (PAG) 64 Ultra Librarian

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