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ADC12QJ1600-SEP

Name: ADC12QJ1600-SEP
Brand: TI
SKU: ADC12QJ1600-SEP
Price: 13500 USD

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Strahlungstoleranter 12-Bit-Vier-Kanal-A/D-Wandler, 30 krad, 1,6 GSPS, mit JESD204C-Schnittstelle

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Datenblatt

document-pdfAcrobat ADC12QJ1600-SEP Quad Channel 1.6-GSPS, 12-Bit, Analog-to-Digital Converter (ADC) with JESD204C Interface datasheet (Englisch) PDF | HTML

ADC12QJ1600-SEP

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Datenblatt

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Produktdetails

Sample rate (max) (Msps)

1600

Resolution (Bits)

12

Number of input channels

4

Interface type

JESD204B, JESD204C

Analog input BW (MHz)

6000

Features

Ultra High Speed

Rating

Space

Peak-to-peak input voltage range (V)

0.8

Power consumption (typ) (mW)

1910

Architecture

Folding Interpolating

SNR (dB)

57.4

ENOB (bit)

9

SFDR (dB)

64

Operating temperature range (°C)

-55 to 125

Input buffer

Yes

Radiation, TID (typ) (krad)

30

Radiation, SEL (MeV·cm2/mg)

43

Sample rate (max) (Msps)

1600

Resolution (Bits)

12

Number of input channels

4

Interface type

JESD204B, JESD204C

Analog input BW (MHz)

6000

Features

Ultra High Speed

Rating

Space

Peak-to-peak input voltage range (V)

0.8

Power consumption (typ) (mW)

1910

Architecture

Folding Interpolating

SNR (dB)

57.4

ENOB (bit)

9

SFDR (dB)

64

Operating temperature range (°C)

-55 to 125

Input buffer

Yes

Radiation, TID (typ) (krad)

30

Radiation, SEL (MeV·cm2/mg)

43

FCCSP (ALR)

144

100 mm² 10 x 10

Radiation Tolerance:
- Total Ionizing Dose (TID): 30 krad (Si)
- Single Event Latchup (SEL): 43 MeV-cm 2/mg
- Single Event Upset (SEU) immune registers
Space-enhanced plastic (space EP):
- Meets ASTM E595 outgassing specification
- Vendor item drawing (VID) V62/22610
- Temperature range: –55°C to 125°C
- One fabrication, assembly, and test site
- Wafer lot traceability
- Extended product life cycle
- Extended product change notification
ADC Core:
- Resolution: 12 Bit
- Maximum sampling rate: 1.6 GSPS
- Non-interleaved architecture
- Internal dither reduces high-order harmonics
Performance specifications (–1 dBFS):
- SNR (100 MHz): 57.4 dBFS
- ENOB (100 MHz): 9.1 Bits
- SFDR (100 MHz): 64 dBc
- Noise floor (–20 dBFS): –147 dBFS
Full-scale input voltage: 800 mV PP-DIFF
Full-power input bandwidth: 6 GHz
JESD204C Serial data interface:
- Support for 2 to 8 total SerDes lanes
- Maximum baud-rate: 17.16 Gbps
- 64B/66B and 8B/10B encoding modes
- Subclass-1 support for deterministic latency
- Compatible with JESD204B receivers
Optional internal sampling clock generation
- Internal PLL and VCO (7.2–8.2 GHz)
SYSREF Windowing eases synchronization
Four clock outputs simplify system clocking
- Reference clocks for FPGA or adjacent ADC
- Reference clock for SerDes transceivers
Timestamp input and output for pulsed systems
Power consumption (1 GSPS): 1.9 W
Power supplies: 1.1 V, 1.9 V

Radiation Tolerance:
- Total Ionizing Dose (TID): 30 krad (Si)
- Single Event Latchup (SEL): 43 MeV-cm 2/mg
- Single Event Upset (SEU) immune registers
Space-enhanced plastic (space EP):
- Meets ASTM E595 outgassing specification
- Vendor item drawing (VID) V62/22610
- Temperature range: –55°C to 125°C
- One fabrication, assembly, and test site
- Wafer lot traceability
- Extended product life cycle
- Extended product change notification
ADC Core:
- Resolution: 12 Bit
- Maximum sampling rate: 1.6 GSPS
- Non-interleaved architecture
- Internal dither reduces high-order harmonics
Performance specifications (–1 dBFS):
- SNR (100 MHz): 57.4 dBFS
- ENOB (100 MHz): 9.1 Bits
- SFDR (100 MHz): 64 dBc
- Noise floor (–20 dBFS): –147 dBFS
Full-scale input voltage: 800 mV PP-DIFF
Full-power input bandwidth: 6 GHz
JESD204C Serial data interface:
- Support for 2 to 8 total SerDes lanes
- Maximum baud-rate: 17.16 Gbps
- 64B/66B and 8B/10B encoding modes
- Subclass-1 support for deterministic latency
- Compatible with JESD204B receivers
Optional internal sampling clock generation
- Internal PLL and VCO (7.2–8.2 GHz)
SYSREF Windowing eases synchronization
Four clock outputs simplify system clocking
- Reference clocks for FPGA or adjacent ADC
- Reference clock for SerDes transceivers
Timestamp input and output for pulsed systems
Power consumption (1 GSPS): 1.9 W
Power supplies: 1.1 V, 1.9 V

ADC12QJ1600-SEP is a quad channel, 12-bit, 1.6 GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the device suited for a variety of mulch-chanel communications systems.

Full-power input bandwidth (-3 dB) of 6 GHz enables direct RF sampling of L-band and S-band.

A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.

JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16 Gbps, to allow the optimal configuration for each application.

ADC12QJ1600-SEP is a quad channel, 12-bit, 1.6 GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the device suited for a variety of mulch-chanel communications systems.

Full-power input bandwidth (-3 dB) of 6 GHz enables direct RF sampling of L-band and S-band.

A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.

JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16 Gbps, to allow the optimal configuration for each application.

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	Typ	Titel		Datum
*	Data sheet	ADC12QJ1600-SEP Quad Channel 1.6-GSPS, 12-Bit, Analog-to-Digital Converter (ADC) with JESD204C Interface datasheet	PDF \| HTML	13 Jan 2023

Design und Entwicklung

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ADC12QJ1600-SEP

Strahlungstoleranter 12-Bit-Vier-Kanal-A/D-Wandler, 30 krad, 1,6 GSPS, mit JESD204C-Schnittstelle

ADC12QJ1600-SEP

Produktdetails

Technische Dokumentation

Design und Entwicklung

ADC12QJ1600EVM — ADC12QJ1600-Q1 4-kanaliger ADC, 12 Bit, 1,6 GSPS, mit JESD204C-Schnittstelle – Evaluierungsmodul

TSW14J57EVM — Datenerfassung/Mustergenerator: Datenwandler-EVM mit 16 JESD204B-Lanes von 1,6–15 Gbps

ADC12QJ1600 IBIS-AMI Model

PSPICE-FOR-TI — PSpice® für TI Design-und Simulationstool

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