ADC3643

AKTIV

Zweikanaliger, 14-Bit, 65 MSPS Analog-Digital-Wandler (ADC) mit geringem Rauschen und extrem geringe

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Datenblatt

document-pdfAcrobat ADC364x 14-bit, 10-MSPS to 65-MSPS, Low-Noise, Low Power Dual Channel ADC datasheet (Rev. A) (Englisch) PDF | HTML

ADC3643

AKTIV

Datenblatt

Jetzt bestellen

Produktdetails

Sample rate (max) (Msps)

65

Resolution (Bits)

14

Number of input channels

2

Interface type

CMOS

Analog input BW (MHz)

900

Features

High Performance, Low Power

Rating

Catalog

Peak-to-peak input voltage range (V)

2.25

Power consumption (typ) (mW)

144

Architecture

SAR

SNR (dB)

79

ENOB (Bits)

12.8

SFDR (dB)

93

Operating temperature range (°C)

-40 to 105

Input buffer

No

Sample rate (max) (Msps)

65

Resolution (Bits)

14

Number of input channels

2

Interface type

CMOS

Analog input BW (MHz)

900

Features

High Performance, Low Power

Rating

Catalog

Peak-to-peak input voltage range (V)

2.25

Power consumption (typ) (mW)

144

Architecture

SAR

SNR (dB)

79

ENOB (Bits)

12.8

SFDR (dB)

93

Operating temperature range (°C)

-40 to 105

Input buffer

No

WQFN (RSB)

40

25 mm² (5 mm × 5 mm)

Dual channel
14-bit 10/25/65 MSPS ADC
Noise floor: –155 dBFS/Hz
Ultra-low power with optimized power scaling: 29 mW/ch (10 MSPS) to 72 mW/ch (65 MSPS)
Latency: 1 clock cycle
14-Bit, no missing codes
INL: ±0.6 LSB; DNL: ±0.2 LSB
Reference: external or internal
Industrial temperature range: –40°C to +105°C
On-chip digital filter (optional)
- Decimation by 2, 4, 8, 16, 32
- 32-bit NCO
DDR and Serial CMOS interface
Small footprint: 40-VQFN (5 mm × 5 mm) package
Single 1.8-V supply
Spectral performance (f_IN = 5 MHz):
- SNR: 79.0 dBFS
- SFDR: 93-dBc HD2, HD3
- SFDR: 101-dBFS worst spur
Spectral performance (f_IN = 64 MHz):
- SNR: 74.0 dBFS
- SFDR: 84-dBc HD2, HD3
- SFDR: 90-dBFS worst spur

Dual channel
14-bit 10/25/65 MSPS ADC
Noise floor: –155 dBFS/Hz
Ultra-low power with optimized power scaling: 29 mW/ch (10 MSPS) to 72 mW/ch (65 MSPS)
Latency: 1 clock cycle
14-Bit, no missing codes
INL: ±0.6 LSB; DNL: ±0.2 LSB
Reference: external or internal
Industrial temperature range: –40°C to +105°C
On-chip digital filter (optional)
- Decimation by 2, 4, 8, 16, 32
- 32-bit NCO
DDR and Serial CMOS interface
Small footprint: 40-VQFN (5 mm × 5 mm) package
Single 1.8-V supply
Spectral performance (f_IN = 5 MHz):
- SNR: 79.0 dBFS
- SFDR: 93-dBc HD2, HD3
- SFDR: 101-dBFS worst spur
Spectral performance (f_IN = 64 MHz):
- SNR: 74.0 dBFS
- SFDR: 84-dBc HD2, HD3
- SFDR: 90-dBFS worst spur

The ADC364x family of devices are low-noise, ultra-low power, 14-bit, 10-MSPS to 65-MSPS dual-channel, high-speed analog-to-digital converters (ADCs). Designed for low power consumption, these devices deliver a noise spectral density of –155 dBFS/Hz, combined with excellent linearity and dynamic range. The ADC364x offers very good dc precision, together with IF sampling support, which make the device an excellent choice for a wide range of applications. High-speed control loops benefit from the short latency of only one clock cycle. The ADC consumes only 72 mW/ch at 65 MSPS, and power consumption scales well with lower sampling rates.

The ADC364x use a DDR or serial CMOS interface to output the data offering lowest power digital interface, together with flexibility to minimize the number of digital interconnects. These devices are a pin-to-pin compatible family with different speed grades. These devices support the extended industrial temperature range of –40 to +105⁰C.

The ADC364x family of devices are low-noise, ultra-low power, 14-bit, 10-MSPS to 65-MSPS dual-channel, high-speed analog-to-digital converters (ADCs). Designed for low power consumption, these devices deliver a noise spectral density of –155 dBFS/Hz, combined with excellent linearity and dynamic range. The ADC364x offers very good dc precision, together with IF sampling support, which make the device an excellent choice for a wide range of applications. High-speed control loops benefit from the short latency of only one clock cycle. The ADC consumes only 72 mW/ch at 65 MSPS, and power consumption scales well with lower sampling rates.

The ADC364x use a DDR or serial CMOS interface to output the data offering lowest power digital interface, together with flexibility to minimize the number of digital interconnects. These devices are a pin-to-pin compatible family with different speed grades. These devices support the extended industrial temperature range of –40 to +105⁰C.

filter

Andere Highspeed-ADCs (≥ 10 MSPS) suchen

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Unsere ADC3660-Familie gewann die World Electronics Achievement Awards (WEAA) 2021 für das Produkt des Jahres in der Kategorie Verstärker/Datenumwandlung.

Technische Dokumentation

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Top-Dokumentation	Typ	Titel	Format-Optionen	Datum
*	Datenblatt	ADC364x 14-bit, 10-MSPS to 65-MSPS, Low-Noise, Low Power Dual Channel ADC datasheet (Rev. A)	PDF \| HTML	20.05.2022
	Anwendungshinweis	Practical Clocking Considerations That Give Your Next High-Speed Converter Design an Edge (Rev. A)	PDF \| HTML	11.04.2025
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	Anwendungshinweis	High-Speed ADC: How to Properly Terminate Single-ended CMOS Digital Outputs		09.12.2020
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	Analog Design Journal	How to simplify AFE filtering via high‐speed ADCs with internal digital filters		10.01.2020

Design und Entwicklung

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