ADS4146

AKTIV

Analog-Digital-Wandler (ADC), 14 Bit 160 MSPS

Jetzt bestellen

Datenblatt

document-pdfAcrobat 12-/14-Bit, 160/250MSPS, Ultralow-Power ADC datasheet (Rev. G) (Englisch)

Benutzerhandbücher

document-pdfAcrobat
Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide) (Englisch)

ADS4146

AKTIV

Jetzt bestellen

Produktdetails

Sample rate (max) (Msps)

160

Resolution (Bits)

14

Number of input channels

1

Interface type

DDR LVDS, Parallel CMOS

Analog input BW (MHz)

800

Features

Low Power

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

200

Architecture

Pipeline

SNR (dB)

72.2

ENOB (Bits)

11.5

SFDR (dB)

88

Operating temperature range (°C)

-40 to 85

Input buffer

No

Sample rate (max) (Msps)

160

Resolution (Bits)

14

Number of input channels

1

Interface type

DDR LVDS, Parallel CMOS

Analog input BW (MHz)

800

Features

Low Power

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

200

Architecture

Pipeline

SNR (dB)

72.2

ENOB (Bits)

11.5

SFDR (dB)

88

Operating temperature range (°C)

-40 to 85

Input buffer

No

VQFN (RGZ)

48

49 mm² (7 mm × 7 mm)

Maximum Sample Rate: 250MSPS
Ultralow Power with 1.8V Single Supply:
- 201mW Total Power at 160MSPS
- 265mW Total Power at 250MSPS
High Dynamic Performance:
- SNR: 70.6dBFS at 170MHz
- SFDR: 84dBc at 170MHz
Dynamic Power Scaling with Sample Rate
Output Interface:
- Double Data Rate (DDR) LVDS with Programmable Swing and Strength
  - Standard Swing: 350mV
  - Low Swing: 200mV
  - Default Strength: 100Ω Termination
  - 2x Strength: 50Ω Termination
- 1.8V Parallel CMOS Interface Also Supported
Programmable Gain up to 6dB for SNR/SFDR Trade-Off
DC Offset Correction
Supports Low Input Clock Amplitude Down To 200mV_PP
Package: QFN-48 (7mm × 7mm)

PowerPAD is a trademark of Texas Instruments Incorporated.
All other trademarks are the property of their respective owners.

Maximum Sample Rate: 250MSPS
Ultralow Power with 1.8V Single Supply:
- 201mW Total Power at 160MSPS
- 265mW Total Power at 250MSPS
High Dynamic Performance:
- SNR: 70.6dBFS at 170MHz
- SFDR: 84dBc at 170MHz
Dynamic Power Scaling with Sample Rate
Output Interface:
- Double Data Rate (DDR) LVDS with Programmable Swing and Strength
  - Standard Swing: 350mV
  - Low Swing: 200mV
  - Default Strength: 100Ω Termination
  - 2x Strength: 50Ω Termination
- 1.8V Parallel CMOS Interface Also Supported
Programmable Gain up to 6dB for SNR/SFDR Trade-Off
DC Offset Correction
Supports Low Input Clock Amplitude Down To 200mV_PP
Package: QFN-48 (7mm × 7mm)

PowerPAD is a trademark of Texas Instruments Incorporated.
All other trademarks are the property of their respective owners.

The ADS412x/4x are a family of 12-bit/14-bit analog-to-digital converters (ADCs) with sampling rates up to 250MSPS. These devices use innovative design techniques to achieve high dynamic performance, while consuming extremely low power at 1.8V supply. The devices are well-suited for multi-carrier, wide bandwidth communications applications.

The ADS412x/4x have fine gain options that can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. They include a dc offset correction loop that can be used to cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled down power with no loss in performance.

The ADS412x/4x are available in a compact QFN-48 package and are specified over the industrial temperature range (–40°C to +85°C)

The ADS412x/4x are a family of 12-bit/14-bit analog-to-digital converters (ADCs) with sampling rates up to 250MSPS. These devices use innovative design techniques to achieve high dynamic performance, while consuming extremely low power at 1.8V supply. The devices are well-suited for multi-carrier, wide bandwidth communications applications.

The ADS412x/4x have fine gain options that can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. They include a dc offset correction loop that can be used to cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled down power with no loss in performance.

The ADS412x/4x are available in a compact QFN-48 package and are specified over the industrial temperature range (–40°C to +85°C)

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Andere Highspeed-ADCs (≥ 10 MSPS) suchen

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Technische Dokumentation

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Alle anzeigen 13

Top-Dokumentation	Typ	Titel
*	Datenblatt	12-/14-Bit, 160/250MSPS, Ultralow-Power ADC datasheet (Rev. G)	20.01.2011
*	Benutzerhandbuch	Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide)	10.07.2012
	Anwendungshinweis	Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)	22.05.2015
	Anwendungshinweis	Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)	19.07.2013
	Anwendungshinweis	Band-Pass Filter Design Techniques for High-Speed ADCs	27.02.2012
	Anwendungshinweis	High-Speed, Analog-to-Digital Converter Basics	11.01.2012
	Anwendungshinweis	Power Supply Design for the ADS41xx (Rev. A)	29.12.2011
	Anwendungshinweis	Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)	10.09.2010
	Anwendungshinweis	Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio	28.04.2009
	Anwendungshinweis	CDCE62005 as Clock Solution for High-Speed ADCs	04.09.2008
	Anwendungshinweis	CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters	08.06.2008
	Anwendungshinweis	Phase Noise Performance and Jitter Cleaning Ability of CDCE72010	02.06.2008
	Anwendungshinweis	QFN Layout Guidelines	28.07.2006

Design und Entwicklung

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