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The ADS41B25 is a member of the ultralow-power ADS4xxx analog-to-digital converter (ADC) family, featuring integrated analog input buffers. This device uses innovative design techniques to achieve high dynamic performance, while consuming extremely low power. The analog input pins have buffers, with the benefits of constant performance and input impedance across a wide frequency range. The device is well-suited for multi-carrier, wide bandwidth communications applications such as PA linearization.
The ADS41B25 has features such as digital gain and offset correction. The gain option can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. The integrated dc offset correction loop can be used to estimate and cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance.
The device supports both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel CMOS digital output interfaces. The low data rate of the DDR LVDS interface (maximum 500MBPS) makes it possible to use low-cost field-programmable gate array (FPGA)-based receivers. The device has a low-swing LVDS mode that can be used to further reduce the power consumption. The strength of the LVDS output buffers can also be increased to support 50Ω differential termination.
The device is available in a compact QFN-48 package and is specified over the industrial temperature range (–40°C to +85°C).
| Top-Dokumentation | Typ | Titel | Format-Optionen | Neueste englische Version herunterladen | Datum | |
|---|---|---|---|---|---|---|
| * | Datenblatt | 12-Bit, 125MSPS Ultra-Low Power ADC with Analog Buffer datasheet | 22.06.2011 | |||
| * | Benutzerhandbuch | Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide) | 10.07.2012 | |||
| Anwendungshinweis | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | 22.05.2015 | ||||
| Anwendungshinweis | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | 19.07.2013 | ||||
| Anwendungshinweis | Band-Pass Filter Design Techniques for High-Speed ADCs | 27.02.2012 | ||||
| Anwendungshinweis | High-Speed, Analog-to-Digital Converter Basics | 11.01.2012 | ||||
| Anwendungshinweis | CDCE62005 as Clock Solution for High-Speed ADCs | 04.09.2008 | ||||
| Anwendungshinweis | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 08.06.2008 | ||||
| Anwendungshinweis | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 02.06.2008 | ||||
| Anwendungshinweis | QFN Layout Guidelines | 28.07.2006 |
Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.
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| Gehäuse | Pins | CAD-Symbole, Footprints und 3D-Modelle |
|---|---|---|
| VQFN (RGZ) | 48 | Ultra Librarian |
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