ADS5527

AKTIV

Analog-Digital-Wandler (ADC), 12 Bit, 210 MSPS

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Datenblatt

document-pdfAcrobat 12-Bit, 210 MSPS ADC With DDR LVDS/CMOS Outputs datasheet (Rev. A) (Englisch)

ADS5527

AKTIV

Jetzt bestellen

Produktdetails

Sample rate (max) (Msps)

210

Resolution (Bits)

12

Number of input channels

1

Interface type

Parallel CMOS, Parallel LVDS

Analog input BW (MHz)

800

Features

Low Power

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

1230

Architecture

Pipeline

SNR (dB)

70.7

ENOB (Bits)

11.4

SFDR (dB)

86

Operating temperature range (°C)

-40 to 85

Input buffer

No

Sample rate (max) (Msps)

210

Resolution (Bits)

12

Number of input channels

1

Interface type

Parallel CMOS, Parallel LVDS

Analog input BW (MHz)

800

Features

Low Power

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

1230

Architecture

Pipeline

SNR (dB)

70.7

ENOB (Bits)

11.4

SFDR (dB)

86

Operating temperature range (°C)

-40 to 85

Input buffer

No

VQFN (RGZ)

48

49 mm² (7 mm × 7 mm)

Maximum Sample Rate: 210 MSPS
12-Bit Resolution
No Missing Codes
Total Power Dissipation 1.23 W
Internal Sample and Hold
70.5-dBFS SNR at 70-MHz IF
84-dBc SFDR at 70-MHz IF, 0-dB gain
High Analog Bandwith up to 800 MHz
Double Data Rate (DDR) LVDS and Parallel CMOS Output Options
Programmable Gain up to 6 dB for SNR/SFDR Trade-Off at High IF
Reduced Power Modes at Lower Sample Rates
Supports Input Clock Amplitude Down to
400 mV_PP
Clock Duty Cycle Stabilizer
No External Reference Decoupling Required
Internal and External Reference Support
Programmable Output Clock Position to Ease Data Capture
3.3-V Analog and Digital Supply
48-QFN Package (7 mm × 7 mm)
APPLICATIONS
- Wireless Communications Infrastructure
- Software Defined Radio
- Power Amplifier Linearization
- 802.16d/e
- Test and Measurement Instrumentation
- High Definition Video
- Medical Imaging
- Radar Systems

Maximum Sample Rate: 210 MSPS
12-Bit Resolution
No Missing Codes
Total Power Dissipation 1.23 W
Internal Sample and Hold
70.5-dBFS SNR at 70-MHz IF
84-dBc SFDR at 70-MHz IF, 0-dB gain
High Analog Bandwith up to 800 MHz
Double Data Rate (DDR) LVDS and Parallel CMOS Output Options
Programmable Gain up to 6 dB for SNR/SFDR Trade-Off at High IF
Reduced Power Modes at Lower Sample Rates
Supports Input Clock Amplitude Down to
400 mV_PP
Clock Duty Cycle Stabilizer
No External Reference Decoupling Required
Internal and External Reference Support
Programmable Output Clock Position to Ease Data Capture
3.3-V Analog and Digital Supply
48-QFN Package (7 mm × 7 mm)
APPLICATIONS
- Wireless Communications Infrastructure
- Software Defined Radio
- Power Amplifier Linearization
- 802.16d/e
- Test and Measurement Instrumentation
- High Definition Video
- Medical Imaging
- Radar Systems

ADS5527 is a high performance 12-bit, 210-MSPS A/D converter. It offers state-of-the art functionality and performance using advanced techniques to minimize board space. With high analog bandwidth and low jitter input clock buffer, the ADC supports both high SNR and high SFDR at high input frequencies. It features programmable gain options that can be used to improve SFDR performance at lower full-scale analog input ranges.

In a compact 48-pin QFN, the device offers fully differential LVDS DDR (Double Data Rate) interface while parallel CMOS outputs can also be selected. Flexible output clock position programmability is available to ease capture and trade-off setup for hold times. At lower sampling rates, the ADC can be operated at scaled down power with no loss in performance. The ADS5527 includes an internal reference, while eliminating the traditional reference pins and associated external decoupling. The device also supports an external reference mode.

The device is specified over the industrial temperature range (-40°C to 85°C).

ADS5527 is a high performance 12-bit, 210-MSPS A/D converter. It offers state-of-the art functionality and performance using advanced techniques to minimize board space. With high analog bandwidth and low jitter input clock buffer, the ADC supports both high SNR and high SFDR at high input frequencies. It features programmable gain options that can be used to improve SFDR performance at lower full-scale analog input ranges.

In a compact 48-pin QFN, the device offers fully differential LVDS DDR (Double Data Rate) interface while parallel CMOS outputs can also be selected. Flexible output clock position programmability is available to ease capture and trade-off setup for hold times. At lower sampling rates, the ADC can be operated at scaled down power with no loss in performance. The ADS5527 includes an internal reference, while eliminating the traditional reference pins and associated external decoupling. The device also supports an external reference mode.

The device is specified over the industrial temperature range (-40°C to 85°C).

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Technische Dokumentation

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Top-Dokumentation	Typ	Titel
*	Datenblatt	12-Bit, 210 MSPS ADC With DDR LVDS/CMOS Outputs datasheet (Rev. A)	07.05.2007
	Anwendungshinweis	Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)	22.05.2015
	Anwendungshinweis	Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)	19.07.2013
	Anwendungshinweis	Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)	10.09.2010
	Anwendungshinweis	Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio	28.04.2009
	Anwendungshinweis	CDCE62005 as Clock Solution for High-Speed ADCs	04.09.2008
	Anwendungshinweis	CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters	08.06.2008
	Anwendungshinweis	Phase Noise Performance and Jitter Cleaning Ability of CDCE72010	02.06.2008
	Anwendungshinweis	QFN Layout Guidelines	28.07.2006

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