ADS5553
Zweikanaliger Analog-zu-Digital-Wandler (ADC), 14 Bit, 65 MSPS
ADS5553
- Dual ADC
- 14 Bit Resolution
- 65 MSPS Sample Rate
- High SNR = 74 dBFs at 70 MHz fIN
- High SFDR = 84 dBc at 70 MHz fIN
- 2.3 VPP Differential Input Voltage
- Internal / External Voltage Reference
- 3.3 V Single-Supply Voltage
- Analog Power Dissipation = 0.72 W
- Output Supply Power Dissipation = 0.17 W
- 80 Lead PowerPad™ TQFP Package
- Two’s Complement Output Format
- APPLICATIONS
- Communication Receivers
- Base Station Infrastructure
- Test and Measurement Instrumentation
PowerPAD and CommsADC are trademarks of Texas Instruments.
The ADS5553 is a high-performance, dual channel, 14 bit, 65 MSPS analog-to-digital converter (ADC). To provide a complete solution, each channel includes a high-bandwidth linear sample-and-hold stage (S& H) and an internal reference. Designed for applications demanding high dynamic performance in a small space, the ADS5553 has excellent power consumption of 0.9 W at 3.3 V single-supply voltage. This allows an even higher system integration density. The provided internal reference simplifies system design requirements, yet an external reference can be used optionally to suit the accuracy and low drift requirements of the application. The outputs are parallel CMOS compatible.
The ADS5553 is available in a 80 lead TQFP PowerPAD package and is specified over the full temperature range of -40°C to 85°C.
Technische Dokumentation
Typ | Titel | Datum | ||
---|---|---|---|---|
* | Data sheet | Dual 14 Bit, 65 MSPS ADC datasheet | 21 Feb 2005 | |
Application note | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | 22 Mai 2015 | ||
Application note | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | 19 Jul 2013 | ||
Application note | Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) | 10 Sep 2010 | ||
Application note | Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio | 28 Apr 2009 | ||
Application note | CDCE62005 as Clock Solution for High-Speed ADCs | 04 Sep 2008 | ||
Application note | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 08 Jun 2008 | ||
Application note | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 02 Jun 2008 | ||
EVM User's guide | ADS5553 EVM | 01 Mär 2005 | ||
Analog Design Journal | Clocking High-Speed Data Converters | 18 Jan 2005 |
Design und Entwicklung
Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.
ANALOG-ENGINEER-CALC — PC software analog engineer's calculator
The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)
Unterstützte Produkte und Hardware
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Präzisionsoperationsverstärker (Vos < 1 mV)
Universal-Operationsverstärker
Audio-Operationsverstärker
Transimpedanzverstärker
Hochgeschwindigkeits-Operationsverstärker (Transitfrequenz ≥ 50 MHz)
Leistungsoperationsverstärker
Videoverstärker
Leitungstreiber
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Voll differenzielle Verstärker
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Differenzverstärker
Instrumentenverstärker
Audio-Leitungsempfänger
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Digitale Leistungsmonitore
Analoge Strommessverstärker mit integriertem Shunt-Widerstand
Digitale Leistungsmonitore mit integriertem Shunt-Widerstand
Die- & Wafer-Services
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JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.
Unterstützte Produkte und Hardware
Produkte
Highspeed-ADCs (≥ 10 MSPS)
Präzisions-ADCs
PSPICE-FOR-TI — PSpice® für TI Design-und Simulationstool
Gehäuse | Pins | CAD-Symbole, Footprints und 3D-Modelle |
---|---|---|
HTQFP (PFP) | 80 | Ultra Librarian |
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