Produktdetails

Sample rate (max) (Msps) 65 Resolution (Bits) 12 Number of input channels 2 Interface type DDR LVDS, Parallel CMOS Analog input BW (MHz) 450 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 518 Architecture Pipeline SNR (dB) 71.6 ENOB (Bits) 11.5 SFDR (dB) 94 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 65 Resolution (Bits) 12 Number of input channels 2 Interface type DDR LVDS, Parallel CMOS Analog input BW (MHz) 450 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 518 Architecture Pipeline SNR (dB) 71.6 ENOB (Bits) 11.5 SFDR (dB) 94 Operating temperature range (°C) -40 to 85 Input buffer No
VQFN (RGC) 64 81 mm² 9 x 9
  • Maximum Sample Rate: 125 MSPS
  • 12-Bit Resolution with No Missing Codes
  • 95 dB Crosstalk
  • Parallel CMOS and DDR LVDS Output Options
  • 3.5 dB Coarse Gain and Programmable Fine Gain
    up to 6 dB for SNR/SFDR Trade-Off
  • Digital Processing Block with:
    • Offset Correction
    • Fine Gain Correction, in Steps of 0.05 dB
    • Decimation by 2/4/8
    • Built-in and Custom Programmable
      24-Tap Low-/High-/Band-Pass Filters
  • Supports Sine, LVPECL, LVDS, and LVCMOS Clocks and
    Amplitude Down to 400 mVPP
  • Clock Duty Cycle Stabilizer
  • Internal Reference; Supports External Reference also
  • 64-QFN Package (9mm × 9mm)
  • Pin Compatible 14-Bit Family (ADS62P4X)
  • Maximum Sample Rate: 125 MSPS
  • 12-Bit Resolution with No Missing Codes
  • 95 dB Crosstalk
  • Parallel CMOS and DDR LVDS Output Options
  • 3.5 dB Coarse Gain and Programmable Fine Gain
    up to 6 dB for SNR/SFDR Trade-Off
  • Digital Processing Block with:
    • Offset Correction
    • Fine Gain Correction, in Steps of 0.05 dB
    • Decimation by 2/4/8
    • Built-in and Custom Programmable
      24-Tap Low-/High-/Band-Pass Filters
  • Supports Sine, LVPECL, LVDS, and LVCMOS Clocks and
    Amplitude Down to 400 mVPP
  • Clock Duty Cycle Stabilizer
  • Internal Reference; Supports External Reference also
  • 64-QFN Package (9mm × 9mm)
  • Pin Compatible 14-Bit Family (ADS62P4X)

ADS62P2X is a dual channel 12-bit A/D converter family with maximum sample rates up to 125 MSPS. It combines high performance and low power consumption in a compact 64 QFN package. Using an internal sample and hold and low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and fine gain options that can be used to improve SFDR performance at lower full-scale input ranges.

ADS62P2X includes a digital processing block that consists of several useful and commonly used digital functions such as ADC offset correction, fine gain correction (in steps of 0.05 dB), decimation by 2,4,8 and in-built and custom programmable filters. By default, the digital processing block is bypassed, and its functions are disabled.

Two output interface options exist – parallel CMOS and DDR LVDS (Double Data Rate). ADS62P2X includes internal references while traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C).

ADS62P2X is a dual channel 12-bit A/D converter family with maximum sample rates up to 125 MSPS. It combines high performance and low power consumption in a compact 64 QFN package. Using an internal sample and hold and low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and fine gain options that can be used to improve SFDR performance at lower full-scale input ranges.

ADS62P2X includes a digital processing block that consists of several useful and commonly used digital functions such as ADC offset correction, fine gain correction (in steps of 0.05 dB), decimation by 2,4,8 and in-built and custom programmable filters. By default, the digital processing block is bypassed, and its functions are disabled.

Two output interface options exist – parallel CMOS and DDR LVDS (Double Data Rate). ADS62P2X includes internal references while traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C).

Herunterladen Video mit Transkript ansehen Video

Ähnliche Produkte, die für Sie interessant sein könnten

Selbe Funktionalität wie der verglichene Baustein bei gleicher Anschlussbelegung
ADS62P42 AKTIV Zweikanaliger Analog-zu-Digital-Wandler (ADC), 14 Bit, 65 MSPS Pin-for-pin 14-bit upgrade

Technische Dokumentation

star =Von TI ausgewählte Top-Empfehlungen für dieses Produkt
Keine Ergebnisse gefunden. Bitte geben Sie einen anderen Begriff ein und versuchen Sie es erneut.
Alle anzeigen 13
Top-Dokumentation Typ Titel Format-Optionen Datum
* Data sheet Dual Channel, 12Bit, 125/105/80/65 MSPS ADC with DDR LVDS/CMOS Outputs datasheet (Rev. C) 11 Mai 2011
Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 22 Mai 2015
Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 19 Jul 2013
User guide TSW4200 Demonstration Kit User's Guide (Rev. C) 31 Okt 2012
User guide Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide) 10 Jul 2012
Application note Band-Pass Filter Design Techniques for High-Speed ADCs 27 Feb 2012
Application note Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) 10 Sep 2010
Application note Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio 28 Apr 2009
User guide ADS62PxxEVM Quick Start Guide (Rev C Board) (Rev. A) 02 Apr 2009
Application note CDCE62005 as Clock Solution for High-Speed ADCs 04 Sep 2008
Application note CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters 08 Jun 2008
Application note Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 02 Jun 2008
Application note QFN Layout Guidelines 28 Jul 2006

Design und Entwicklung

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.

GUI für Evaluierungsmodul (EVM)

DATACONVERTERPRO-SW High Speed Data Converter Pro GUI Installer, v5.31

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)

Unterstützte Produkte und Hardware

Unterstützte Produkte und Hardware

Support-Software

HSADC-SPI-UTILITY ADS5400 EVM GUI

Unterstützte Produkte und Hardware

Unterstützte Produkte und Hardware

Simulationsmodell

ADS62Pxx Family TINA-TI Transient Reference Design

SBAM008.ZIP (6 KB) - TINA-TI Reference Design
Simulationsmodell

ADS62Pxx Family TINA-TI Transient Spice Model

SBAM007.TSM (14 KB) - TINA-TI Spice Model
Simulationsmodell

ADS62Pxx IBIS Model (Rev. A)

SLAC176A.ZIP (921 KB) - IBIS Model
Berechnungstool

ADC-HARMONIC-CALC ADC Frequency Calculator Download

    The ADC Harmonic Calculation tool is an excel based calculator for determining the location in frequency space of high order harmonics following Nyquist aliasing in an analog to digital converter.

    Given an ADC sample rate and the span of a signal of interest the calcultor will determine if the 2nd (...)

Unterstützte Produkte und Hardware

Unterstützte Produkte und Hardware

Berechnungstool

ANALOG-ENGINEER-CALC PC software analog engineer's calculator

The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)

Unterstützte Produkte und Hardware

Unterstützte Produkte und Hardware

Designtool

SBAC119 TIGAR (Texas Instruments Graphical Evaluation of ADC Response Tool)

Unterstützte Produkte und Hardware

Unterstützte Produkte und Hardware

Simulationstool

PSPICE-FOR-TI — PSpice® für TI Design-und Simulationstool

PSpice® für TI ist eine Design- und Simulationsumgebung, welche Sie dabei unterstützt, die Funktionalität analoger Schaltungen zu evaluieren. Diese Design- und Simulationssuite mit vollem Funktionsumfang verwendet eine analoge Analyse-Engine von Cadence®. PSpice für TI ist kostenlos erhältlich und (...)
Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
VQFN (RGC) 64 Ultra Librarian

Bestellen & Qualität

Beinhaltete Information:
  • RoHS
  • REACH
  • Bausteinkennzeichnung
  • Blei-Finish/Ball-Material
  • MSL-Rating / Spitzenrückfluss
  • MTBF-/FIT-Schätzungen
  • Materialinhalt
  • Qualifikationszusammenfassung
  • Kontinuierliches Zuverlässigkeitsmonitoring
Beinhaltete Information:
  • Werksstandort
  • Montagestandort

Support und Schulungen

TI E2E™-Foren mit technischem Support von TI-Ingenieuren

Inhalte werden ohne Gewähr von TI und der Community bereitgestellt. Sie stellen keine Spezifikationen von TI dar. Siehe Nutzungsbedingungen.

Bei Fragen zu den Themen Qualität, Gehäuse oder Bestellung von TI-Produkten siehe TI-Support. ​​​​​​​​​​​​​​

Videos