ADS62P28

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Zweikanaliger Analog-zu-Digital-Wandler (ADC), 12 Bit, 210 MSPS

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Datenblatt

document-pdfAcrobat Dual Channel 14-/12-Bit, 250/210 MSPS ADC with DDR LVDS & Parallel CMOS Outputs datasheet (Rev. B) (Englisch)

Benutzerhandbücher

document-pdfAcrobat
Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide) (Englisch)

ADS62P28

AKTIV

Jetzt bestellen

Produktdetails

Sample rate (max) (Msps)

210

Resolution (Bits)

12

Number of input channels

2

Interface type

DDR LVDS, Parallel CMOS

Analog input BW (MHz)

700

Features

High Performance

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

1140

Architecture

Pipeline

SNR (dB)

70.8

ENOB (Bits)

11.1

SFDR (dB)

98

Operating temperature range (°C)

-40 to 85

Input buffer

No

Sample rate (max) (Msps)

210

Resolution (Bits)

12

Number of input channels

2

Interface type

DDR LVDS, Parallel CMOS

Analog input BW (MHz)

700

Features

High Performance

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

1140

Architecture

Pipeline

SNR (dB)

70.8

ENOB (Bits)

11.1

SFDR (dB)

98

Operating temperature range (°C)

-40 to 85

Input buffer

No

VQFN (RGC)

64

81 mm² (9 mm × 9 mm)

Maximum Sample Rate: 250 MSPS
14-Bit Resolution – ADS62P49/ADS62P48
12-Bit Resolution – ADS62P29/ADS62P28
Total Power: 1.25 W at 250 MSPS
Double Data Rate (DDR) LVDS and Parallel CMOS Output Options
Programmable Gain up to 6dB for SNR/SFDR Trade-Off
DC Offset Correction
90dB Cross-Talk
Supports Input Clock Amplitude Down to 400 mV_PP Differential
Internal and External Reference Support
64-QFN Package (9 mm × 9 mm)

Maximum Sample Rate: 250 MSPS
14-Bit Resolution – ADS62P49/ADS62P48
12-Bit Resolution – ADS62P29/ADS62P28
Total Power: 1.25 W at 250 MSPS
Double Data Rate (DDR) LVDS and Parallel CMOS Output Options
Programmable Gain up to 6dB for SNR/SFDR Trade-Off
DC Offset Correction
90dB Cross-Talk
Supports Input Clock Amplitude Down to 400 mV_PP Differential
Internal and External Reference Support
64-QFN Package (9 mm × 9 mm)

The ADS62Px9/x8 is a family of dual channel 14-bit and 12-bit A/D converters with sampling rates up to 250 MSPS. It combines high dynamic performance and low power consumption in a compact 64 QFN package. This makes it well-suited for multi-carrier, wide band-width communications applications.

The ADS62Px9/x8 has gain options that can be used to improve SFDR performance at lower full-scale input ranges. It includes a dc offset correction loop that can be used to cancel the ADC offset. Both DDR LVDS (Double Data Rate) and parallel CMOS digital output interfaces are available.

It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C).

The ADS62Px9/x8 is a family of dual channel 14-bit and 12-bit A/D converters with sampling rates up to 250 MSPS. It combines high dynamic performance and low power consumption in a compact 64 QFN package. This makes it well-suited for multi-carrier, wide band-width communications applications.

The ADS62Px9/x8 has gain options that can be used to improve SFDR performance at lower full-scale input ranges. It includes a dc offset correction loop that can be used to cancel the ADC offset. Both DDR LVDS (Double Data Rate) and parallel CMOS digital output interfaces are available.

It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C).

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Technische Dokumentation

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Top-Dokumentation	Typ	Titel
*	Datenblatt	Dual Channel 14-/12-Bit, 250/210 MSPS ADC with DDR LVDS & Parallel CMOS Outputs datasheet (Rev. B)	04.01.2011
*	Benutzerhandbuch	Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide)	10.07.2012
	Anwendungshinweis	Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)	22.05.2015
	Anwendungshinweis	Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)	19.07.2013
	Benutzerhandbuch	TSW4200 Demonstration Kit User's Guide (Rev. C)	31.10.2012
	Anwendungshinweis	Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)	10.09.2010
	Anwendungshinweis	Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio	28.04.2009
	Anwendungshinweis	CDCE62005 as Clock Solution for High-Speed ADCs	04.09.2008
	Anwendungshinweis	CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters	08.06.2008
	Anwendungshinweis	Phase Noise Performance and Jitter Cleaning Ability of CDCE72010	02.06.2008
	Anwendungshinweis	QFN Layout Guidelines	28.07.2006

Design und Entwicklung

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