ADS6445-EP
Vierkanaliger Analog-Digital-Wandler (ADC), 14 Bit, 125 MSPS – verbessertes Produkt
ADS6445-EP
- Maximum Sample Rate: 125 MSPS
- 14-Bit Resolution with No Missing Codes
- Simultaneous Sample and Hold
- 3.5-dB Coarse Gain and up to 6-dB Programmable
Fine Gain for SFDR/SNR Trade-Off - Serialized LVDS Outputs with Programmable
Internal Termination Option - Supports Sine, LVCMOS, LVPECL, LVDS Clock
Inputs and Amplitude Down to 400 mVPP - Internal Reference with External Reference Support
- No External Decoupling Required for References
- 3.3-V Analog and Digital Supply
- 64-pin QFN Package (9 mm × 9 mm)
- Feature Compatible Dual Channel Family
The ADS6445/ADS6444 is a high performance 14 bit 125/105 MSPS quad channel A-D converter. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 64-pin QFN package (9 mm × 9 mm) that allows for high system integration density. The device includes 3.5 dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1 dB steps up to 6 dB.
The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1 Gbps easing receiver design. The ADS644X also includes the traditional 1-wire interface that can be used at lower sampling frequencies.
An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit clock is used to serialize the 14 bit data from each channel. In addition to the serial data streams, the frame and bit clocks also are transmitted as LVDS outputs.
The LVDS output buffers have features such as programmable LVDS currents, current doubling modes and internal termination options. These can be used to widen eye openings and improve signal integrity, easing capture by the receiver.
The ADC channel outputs can be transmitted either as MSB or LSB first and 2s complement or straight binary.
The ADS644X has internal references, but also can support an external reference mode. The device is specified over –55°C to 125°C operating junction temperature range.
Technische Dokumentation
Typ | Titel | Datum | ||
---|---|---|---|---|
* | Data sheet | QUAD CHANNEL, 14 BIT, 125/105 MSPS ADC WITH SERIAL LVDS OUTPUTS datasheet (Rev. C) | 29 Mai 2013 | |
* | Radiation & reliability report | ADS6445MRGCTEP Reliability Report | 22 Dez 2014 | |
Application note | Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) | 10 Sep 2010 | ||
Application note | Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio | 28 Apr 2009 | ||
Application note | CDCE62005 as Clock Solution for High-Speed ADCs | 04 Sep 2008 | ||
Application note | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 08 Jun 2008 | ||
Application note | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 02 Jun 2008 | ||
Application note | QFN Layout Guidelines | 28 Jul 2006 |
Design und Entwicklung
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VQFN (RGC) | 64 | Ultra Librarian |
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