Produktdetails

Resolution (Bits) 16 Sample rate (max) (ksps) 500 Number of input channels 1 Interface type SPI Architecture SAR Input type Single-ended Rating Catalog Reference mode External Input voltage range (max) (V) 5.5 Input voltage range (min) (V) 0 Features Daisy-Chainable, Small Size Operating temperature range (°C) -40 to 85 Power consumption (typ) (mW) 18 Analog supply voltage (min) (V) 4.5 Analog supply voltage (max) (V) 5.5 SNR (dB) 93.9 Digital supply (min) (V) 2.375 Digital supply (max) (V) 5.5
Resolution (Bits) 16 Sample rate (max) (ksps) 500 Number of input channels 1 Interface type SPI Architecture SAR Input type Single-ended Rating Catalog Reference mode External Input voltage range (max) (V) 5.5 Input voltage range (min) (V) 0 Features Daisy-Chainable, Small Size Operating temperature range (°C) -40 to 85 Power consumption (typ) (mW) 18 Analog supply voltage (min) (V) 4.5 Analog supply voltage (max) (V) 5.5 SNR (dB) 93.9 Digital supply (min) (V) 2.375 Digital supply (max) (V) 5.5
VSON (DRC) 10 9 mm² 3 x 3 VSSOP (DGS) 10 14.7 mm² 3 x 4.9
  • 500-kHz Sample Rate
  • 16-Bit Resolution
  • Zero Latency at Full Speed
  • Unipolar, Single-Ended Input Range: 0 V to VREF
  • SPI-Compatible Serial Interface With Daisy-Chain Option
  • Excellent Performance:
    • 93.6-dB SNR (Typical) at 10-kHz Input
    • –106-dB THD (Typical) at 10-kHz Input
    • ±1.5-LSB (Maximum) INL
    • ±1-LSB (Maximum) DNL
  • Low Power Dissipation: 18 mW (Typical) at 500 kSPS
  • Power Scales Linearly with Speed: 3.6 mW / 100 kSPS
  • Power Dissipation During Power-Down State: 0.25 µW (Typical)
  • 10-Pin VSSOP and VSON Packages
  • 500-kHz Sample Rate
  • 16-Bit Resolution
  • Zero Latency at Full Speed
  • Unipolar, Single-Ended Input Range: 0 V to VREF
  • SPI-Compatible Serial Interface With Daisy-Chain Option
  • Excellent Performance:
    • 93.6-dB SNR (Typical) at 10-kHz Input
    • –106-dB THD (Typical) at 10-kHz Input
    • ±1.5-LSB (Maximum) INL
    • ±1-LSB (Maximum) DNL
  • Low Power Dissipation: 18 mW (Typical) at 500 kSPS
  • Power Scales Linearly with Speed: 3.6 mW / 100 kSPS
  • Power Dissipation During Power-Down State: 0.25 µW (Typical)
  • 10-Pin VSSOP and VSON Packages

The ADS8319 device is a 16-bit, 500-kSPS, analog-to-digital converter (ADC) that operates with a 2.25-V to 5.5-V external reference. The device includes a capacitor-based, successive-approximation register (SAR) ADC with inherent sample and hold.

The device includes a 50-MHz, SPI-compatible serial interface. The interface is designed to support daisy-chaining or cascading of multiple devices. Furthermore, a Busy Indicator makes synchronizing with the digital host easy.

The device unipolar, single-ended input range supports an input swing of 0 V to +VREF.

Device operation is optimized for very-low power operation and the power consumption directly scales with speed. This feature makes the device attractive for lower-speed applications. The device is available in 10-pin VSSOP and VSON packages.

The ADS8319 device is a 16-bit, 500-kSPS, analog-to-digital converter (ADC) that operates with a 2.25-V to 5.5-V external reference. The device includes a capacitor-based, successive-approximation register (SAR) ADC with inherent sample and hold.

The device includes a 50-MHz, SPI-compatible serial interface. The interface is designed to support daisy-chaining or cascading of multiple devices. Furthermore, a Busy Indicator makes synchronizing with the digital host easy.

The device unipolar, single-ended input range supports an input swing of 0 V to +VREF.

Device operation is optimized for very-low power operation and the power consumption directly scales with speed. This feature makes the device attractive for lower-speed applications. The device is available in 10-pin VSSOP and VSON packages.

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Technische Dokumentation

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Top-Dokumentation Typ Titel Format-Optionen Datum
* Data sheet ADS8319 16-Bit, 500-kSPS, Serial Interface, Micropower, Miniature, SAR Analog-to-Digital Converter datasheet (Rev. C) PDF | HTML 09 Dez 2016
Circuit design Antialiasing filter circuit design for single-ended ADC input using fixed cutoff (Rev. B) PDF | HTML 24 Sep 2024
Circuit design Circuit for protecting low-voltage SAR ADC from electrical overstress with minim (Rev. A) PDF | HTML 19 Sep 2024
White paper Voltage-reference impact on total harmonic distortion 01 Aug 2016
More literature SAR ADCs for PLC Applications 11 Feb 2016
E-book Best of Baker's Best: Precision Data Converters -- SAR ADCs 21 Mai 2015
Application note Determining Minimum Acquisition Times for SAR ADCs, part 2 17 Mär 2011
Analog Design Journal The IBIS model, Part 2: Determining the total quality of an IBIS model 14 Mär 2011
Application note Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A) 10 Nov 2010
Application note Low Power Input and Reference Driver Circuit for ADS8318 and ADS8319 24 Jun 2009

Design und Entwicklung

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