AFE8092
HF-Abtasttransceiver mit 8 Sende-, 8 Empfangskanälen, 600 MHz bis 6 GHz, max. 1200 MHz IBW
AFE8092
- Octal RF sampling 12GSPS transmit DACs
- Octal RF sampling 3GSPS receive ADCs
- Maximum RF signal bandwidth:
- TX/FB: 800MHz
- 1200MHz in 4-channel mode
- RX: 600MHz
- TX/FB: 800MHz
- RF frequency range: up to 6GHz
- Digital Step Attenuators (DSA):
- TX: 40dB range, 1dB analog and 0.125dB digital steps
- RX/FB: 31/25dB range, 1dB step
- Single DUC/DDC per chain
- Dual NCOs per chain for fast frequency switching
- Supports TDD operation with fast switching between TX and RX
- Internal PLL/VCO to generate DAC/ADC clocks
- Optional external CLK at DAC or ADC rate
- SerDes data interface:
- JESD204B and JESD204C
- 8 SerDes transceivers up to 32.5Gbps
- 8b/10b and 64b/66b Encoding
- 12-bit, 16-bit, 24-bit and 32-bit resolution
- Subclass one multi-device synchronization
- Package:
- 17mm × 17mm FCBGA, 0.8mm pitch
The AFE8092 is a high performance, wide bandwidth multi-channel transceiver, integrating eight RF sampling transmitter chains, eight RF sampling receiver chains and two separate RF front end for the auxiliary chains (feedback paths). The high dynamic range of the transmitter and receiver chains allows generating and receiving 3G, 4G and 5G signals for wireless base stations, and the AFE8092 wide bandwidth capability is designed for multi-band 4G and 5G base stations.
Each receiver chain includes a 31dB range DSA (Digital Step Attenuator), followed by a 3GSPS ADC (analog-to-digital converter). Each receiver channel has analog peak power detectors and digital peak and power detectors to assist an external or internal autonomous automatic gain controller, and RF overload detectors for device reliability protection. The digital down converters (DDC) provides up to 800MHz of combined signal BW in 8-channel mode and 800MHz in 4-channel mode. In TDD mode, the receiver channel can be configured to dynamically switching between traffic receiver (TDD RX) and wideband feedback receiver (TDD FB), with the capability of re-using the same analog input for both purposes.
Each transmitter chain includes a digital up converter (DUC) supporting up to 800MHz combined signal bandwidth (1200MHz in 4-channel mode). The output of the DUC drives a 12GSPS DAC (digital to analog converter) with a mixed mode output option to enhance 2nd Nyquist operation. The DAC output includes a variable gain amplifier (TX DSA) with 40dB range and 1dB analog and 0.125dB digital steps.
The feedback path includes a 25dB range DSA driving a 3GSPS RF sampling ADC, shared with receiver chain, followed by a DDC with up to 800MHz bandwidth (1200MHz in 4-channel mode).
Weitere Informationen anfordern
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Für alle anderen Anwendungen sehen Sie sich unsere universalen HF-Abtast-AFEs an.
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Technische Dokumentation
| Typ | Titel | Datum | ||
|---|---|---|---|---|
| * | Data sheet | AFE8092 Octal-Channel RF Transceiver with Feedback Paths datasheet (Rev. B) | PDF | HTML | 06 Nov 2024 |
| Application note | RF Sampling Resource Guide | PDF | HTML | 05 Mär 2024 | |
| User guide | Interfacing AFE7769DEVM With the Hitek Agilex eSOM7 FPGA | PDF | HTML | 28 Sep 2023 | |
| Application note | Correcting the External and Internal RF Droop for RF Transmitters | PDF | HTML | 18 Aug 2023 | |
| Application note | Demystifying and Mitigating Power Supply Ripple and Noise Implication on AFE8092 (Rev. B) | PDF | HTML | 16 Nov 2021 | |
| Application note | Temp Profile to Maintain Optimum FIT Performance | 23 Jul 2019 |
Design und Entwicklung
Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.
HTK-3P-AGILEX-ESOM7 — HITEK Agilex eSOM7 with FMC+ connector to RF transceiver EVMs
The Hitek Systems eSOM7 interfaces with the AFE8092, AFE8030, AFE7952, and AFE7920 through an FPGA mezzanine card (FMC) connector. It provides a quick evaluation and prototyping platform for 5G wireless solutions based on Intel’s latest high-performance 10-nm Agilex F-Series FPGA.
TI204C-IP — Request for JESD204 rapid design IP
The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
Unterstützte Produkte und Hardware
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HF-Transceiver
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| Gehäuse | Pins | CAD-Symbole, Footprints und 3D-Modelle |
|---|---|---|
| FCBGA (ABJ) | 400 | Ultra Librarian |
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