Startseite Energiemanagement AC/DC- und DC/DC-Controller (externer FET)

LM25115

AKTIV

Sekundärseitiger Post-Regulator/Synchron-Abwärtsregler, 42 V

Produktdetails

Vin (min) (V) 4.5 Vin (max) (V) 42 Operating temperature range (°C) -40 to 125 Control mode Voltage mode, current mode Rating Catalog Vout (min) (V) 0.75 Vout (max) (V) 13.5 Features Frequency synchronization Duty cycle (max) (%) 85 Number of phases 1
Vin (min) (V) 4.5 Vin (max) (V) 42 Operating temperature range (°C) -40 to 125 Control mode Voltage mode, current mode Rating Catalog Vout (min) (V) 0.75 Vout (max) (V) 13.5 Features Frequency synchronization Duty cycle (max) (%) 85 Number of phases 1
TSSOP (PW) 16 32 mm² 5 x 6.4 WSON (NHQ) 16 25 mm² 5 x 5
  • Self-synchronization to Main Channel Output
  • Free-run Mode for Buck Regulation of DC Input
  • Leading Edge Pulse Width Modulation
  • Voltage-mode Control with Current Injection and Input Line Feed-forward
  • Operates from AC or DC Input up to 42V
  • Wide 4.5V to 30V Bias Supply Range
  • Wide 0.75V to 13.5V Output Range.
  • Top and Bottom Gate Drivers Sink 2.5A Peak
  • Adaptive Gate Driver Dead-time Control
  • Wide Bandwidth Error Amplifier (4MHz)
  • Programmable Soft-start
  • Thermal Shutdown Protection
  • TSSOP-16 or Thermally Enhanced WSON-16 Packages

All trademarks are the property of their respective owners.

  • Self-synchronization to Main Channel Output
  • Free-run Mode for Buck Regulation of DC Input
  • Leading Edge Pulse Width Modulation
  • Voltage-mode Control with Current Injection and Input Line Feed-forward
  • Operates from AC or DC Input up to 42V
  • Wide 4.5V to 30V Bias Supply Range
  • Wide 0.75V to 13.5V Output Range.
  • Top and Bottom Gate Drivers Sink 2.5A Peak
  • Adaptive Gate Driver Dead-time Control
  • Wide Bandwidth Error Amplifier (4MHz)
  • Programmable Soft-start
  • Thermal Shutdown Protection
  • TSSOP-16 or Thermally Enhanced WSON-16 Packages

All trademarks are the property of their respective owners.

The LM25115 controller contains all of the features necessary to implement multiple output power converters utilizing the Secondary Side Post Regulation (SSPR) technique. The SSPR technique develops a highly efficient and well regulated auxiliary output from the secondary side switching waveform of an isolated power converter. Regulation of the auxiliary output voltage is achieved by leading edge pulse width modulation (PWM) of the main channel duty cycle. Leading edge modulation is compatible with either current mode or voltage mode control of the main output. The LM25115 drives external high side and low side NMOS power switches configured as a synchronous buck regulator. A current sense amplifier provides overload protection and operates over a wide common mode input range. Additional features include a low dropout (LDO) bias regulator, error amplifier, precision reference, adaptive dead time control of the gate signals and thermal shutdown.

The LM25115 controller contains all of the features necessary to implement multiple output power converters utilizing the Secondary Side Post Regulation (SSPR) technique. The SSPR technique develops a highly efficient and well regulated auxiliary output from the secondary side switching waveform of an isolated power converter. Regulation of the auxiliary output voltage is achieved by leading edge pulse width modulation (PWM) of the main channel duty cycle. Leading edge modulation is compatible with either current mode or voltage mode control of the main output. The LM25115 drives external high side and low side NMOS power switches configured as a synchronous buck regulator. A current sense amplifier provides overload protection and operates over a wide common mode input range. Additional features include a low dropout (LDO) bias regulator, error amplifier, precision reference, adaptive dead time control of the gate signals and thermal shutdown.

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Technische Dokumentation

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Typ Titel Datum
* Data sheet LM25115 Secondary Side Post Regulator Controller datasheet (Rev. A) 01 Apr 2013
White paper Valuing wide VIN, low EMI synchronous buck circuits for cost-driven, demanding a (Rev. A) 10 Apr 2019
Selection guide Power Management Guide 2018 (Rev. R) 25 Jun 2018
Analog Design Journal Reduce buck-converter EMI and voltage stress by minimizing inductive parasitics 21 Jul 2016
EVM User's guide AN-1368 LM5115/5025A Evaluation Board (Rev. A) 26 Apr 2013
EVM User's guide AN-1367 LM5115 HV DC Evaluation Board (Rev. B) 24 Apr 2013
EVM User's guide AN-1542 LM5115A Evaluation Board (Rev. B) 24 Apr 2013
Application note Minimizing FET Losses For a High Input Rail Buck Converter (Rev. A) 23 Apr 2013

Design und Entwicklung

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.

Simulationsmodell

LM25115 Unencrypted PSpice Transient Model

SNVM861.ZIP (5 KB) - PSpice Model
Simulationsmodell

LM25115 Unencrypted PSpice Transient Model Package (Rev. A)

SNVM511A.ZIP (56 KB) - PSpice Model
Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
TSSOP (PW) 16 Ultra Librarian
WSON (NHQ) 16 Ultra Librarian

Bestellen & Qualität

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  • Blei-Finish/Ball-Material
  • MSL-Rating / Spitzenrückfluss
  • MTBF-/FIT-Schätzungen
  • Materialinhalt
  • Qualifikationszusammenfassung
  • Kontinuierliches Zuverlässigkeitsmonitoring
Beinhaltete Information:
  • Werksstandort
  • Montagestandort

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