Gehäuseinformationen
| Gehäuse | Pins DSBGA (YFP) | 8 |
| Betriebstemperaturbereich (°C) -40 to 125 |
| Gehäusemenge | Träger 3.000 | LARGE T&R |
Merkmale von SN74AUP2G08
- Wide operating VCC range of 0.8V to 3.6V
- Low static-power consumption (ICC = 0.9µA max)
- Low dynamic-power consumption (Cpd = 4.3pF typ at 3.3V)
- Low noise – overshoot and undershoot <10% of VCC
- Ioff supports partial-power-down mode operation
- Schmitt-trigger action allows slow input transition and better switching noise immunity at the input (Vhys = 250mV Typ at 3.3V)
- 3.6V I/O tolerant to support mixed-mode signal operation
- tpd = 5.9ns max at 3.3V
- Latch-up performance exceeds 100mA per JESD 78, Class II
Beschreibung von SN74AUP2G08
This dual 2-input positive-AND gate is designed for 0.8V to 3.6V VCC operation and performs the Boolean function Y = A ● B in positive logic.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when VCC = 0V, preventing damaging current backflow through the device when it is powered down.