Gehäuseinformationen
| Gehäuse | Pins SOIC (D) | 16 |
| Betriebstemperaturbereich (°C) -40 to 125 |
| Gehäusemenge | Träger 2.500 | LARGE T&R |
Merkmale von SN74LV123A
- 2-V to 5.5-V VCC Operation
- Maximum tpd of 11 ns at 5 V
- Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C - Typical VOHV (Output VOH Undershoot)
> 2.3 V at VCC = 3.3 V, TA = 25°C - Support Mixed-Mode Voltage Operation on
All Ports - Schmitt-Trigger Circuitry on A, B, and CLR Inputs
for Slow Input Transition Rates - Edge Triggered From Active-High or
Active-Low Gated Logic Inputs - Ioff Supports Partial-Power-Down Mode Operation
- Retriggerable for Very Long Output Pulses,
up to 100% Duty Cycle - Overriding Clear Terminates Output Pulse
- Glitch-Free Power-Up Reset on Outputs
- Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class 11 - ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
Beschreibung von SN74LV123A
The ’LV123A devices are dual retriggerable monostable multivibrators designed for 2-V to 5.5-V VCC operation.
These edge-triggered multivibrators feature output pulse-duration control by three methods. In the first method, the A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes low. In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.
The output pulse duration is programmable by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR low.