Gehäuseinformationen
| Gehäuse | Pins VSSOP (DCU) | 8 |
| Betriebstemperaturbereich (°C) -40 to 125 |
| Gehäusemenge | Träger 250 | SMALL T&R |
Merkmale von SN74LVC1G123
- Available in the Texas Instruments
NanoFree™ Package - Supports 5-V VCC Operation
- Inputs Accept Voltages to 5.5 V
- Max tpd of 8 ns at 3.3 V
- Supports Mixed-Mode Voltage Operation on
All Ports - Supports Down Translation to VCC
- Schmitt-Trigger Circuitry on A and B Inputs for
Slow Input Transition Rates - Edge Triggered From Active-High or Active-Low
Gated Logic Inputs - Retriggerable for Very Long Output Pulses, Up to
100% Duty Cycle - Overriding Clear Terminates Output Pulse
- Glitch-Free Power-Up Reset on Outputs
- Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection - Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II - ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
Beschreibung von SN74LVC1G123
The SN74LVC1G123 device is a single retriggerable monostable multivibrator designed for 1.65-V to 5.5-V VCC operation.
This monostable multivibrator features output pulse-duration control by three methods. In the first method, the A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes low. In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.
The output pulse duration is programmed by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR low.
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. The A and B inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition rates with jitter-free triggering at the outputs.