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SN74LVC1G123

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Wiederauslösbarer monostabiler Einfach-Multivibrator mit Schmitt-Trigger-Eingängen

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SN74LVC1G123

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Produktdetails

Number of channels 1 Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 5.5 Technology family LVC Input type Schmitt-Trigger Output type Push-Pull Supply current (µA) 20 IOL (max) (mA) 32 IOH (max) (mA) -32 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff) Operating temperature range (°C) -40 to 125 Rating Catalog
Number of channels 1 Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 5.5 Technology family LVC Input type Schmitt-Trigger Output type Push-Pull Supply current (µA) 20 IOL (max) (mA) 32 IOH (max) (mA) -32 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff) Operating temperature range (°C) -40 to 125 Rating Catalog
DSBGA (YZP) 8 2.8125 mm² 2.25 x 1.25 SSOP (DCT) 8 11.8 mm² 2.95 x 4 VSSOP (DCU) 8 6.2 mm² 2 x 3.1
  • Available in the Texas Instruments NanoFree™ Package
  • Supports 5V VCC Operation
  • Inputs Accept Voltages to 5.5V
  • Max tpd of 8ns at 3.3V
  • Supports Mixed-Mode Voltage Operation on All Ports
  • Supports Down Translation to VCC
  • Schmitt-Trigger Circuitry on A and B Inputs for Slow Input Transition Rates
  • Edge Triggered From Active-High or Active-Low Gated Logic Inputs
  • Retriggerable for Very Long Output Pulses, Up to 100% Duty Cycle
  • Overriding Clear Terminates Output Pulse
  • Glitch-Free Power-Up Reset on Outputs
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000V Human-Body Model (A114-A)
    • 200V Machine Model (A115-A)
    • 1000V Charged-Device Model (C101)
  • Available in the Texas Instruments NanoFree™ Package
  • Supports 5V VCC Operation
  • Inputs Accept Voltages to 5.5V
  • Max tpd of 8ns at 3.3V
  • Supports Mixed-Mode Voltage Operation on All Ports
  • Supports Down Translation to VCC
  • Schmitt-Trigger Circuitry on A and B Inputs for Slow Input Transition Rates
  • Edge Triggered From Active-High or Active-Low Gated Logic Inputs
  • Retriggerable for Very Long Output Pulses, Up to 100% Duty Cycle
  • Overriding Clear Terminates Output Pulse
  • Glitch-Free Power-Up Reset on Outputs
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000V Human-Body Model (A114-A)
    • 200V Machine Model (A115-A)
    • 1000V Charged-Device Model (C101)

The SN74LVC1G123 device is a single retriggerable monostable multivibrator designed for 1.65V to 5.5V VCC operation.

This monostable multivibrator features output pulse-duration control by three methods. In the first method, the A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes low. In the third method, the A input is low, the B input is high, and the clear ( CLR) input goes high.

The output pulse duration is programmed by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR low.

Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. The A and B inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition rates with jitter-free triggering at the outputs.

The SN74LVC1G123 device is a single retriggerable monostable multivibrator designed for 1.65V to 5.5V VCC operation.

This monostable multivibrator features output pulse-duration control by three methods. In the first method, the A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes low. In the third method, the A input is low, the B input is high, and the clear ( CLR) input goes high.

The output pulse duration is programmed by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR low.

Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. The A and B inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition rates with jitter-free triggering at the outputs.
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Technische Dokumentation

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Top-Dokumentation Typ Titel Format-Optionen Datum
* Data sheet SN74LVC1G123 Single Retriggerable Monostable Multivibrator With Schmitt-Trigger Inputs datasheet (Rev. E) PDF | HTML 01 Mär 2024
Selection guide Logic Guide (Rev. AC) PDF | HTML 13 Nov 2025
Product overview Configurable Timed Reset Using Discrete Logic (Rev. A) PDF | HTML 02 Mai 2023
Application note The Davies Sinusoidal Generator PDF | HTML 31 Okt 2022
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Application note Designing With the SN74LVC1G123 Monostable Multivibrator (Rev. A) PDF | HTML 13 Mär 2020
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dez 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Product overview Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 06 Nov 2003
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 18 Dez 2002
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 Jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 Mai 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 Mai 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 27 Mär 2002
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dez 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note LVC Characterization Information 01 Dez 1996
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Okt 1996
Application note Live Insertion 01 Okt 1996
Design guide Low-Voltage Logic (LVC) Designer's Guide 01 Sep 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 Mai 1996

Design und Entwicklung

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SN74LVC1G123 IBIS Model

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