ADC10D1000

ACTIVO

Convertidor analógico a digital (ADC) de 10 bits, 1,0 GSPS dobles o 2,0 GSPS simples

Detalles del producto

Sample rate (max) (Msps) 1000, 2000 Resolution (Bits) 10 Number of input channels 1, 2 Interface type Parallel LVDS Analog input BW (MHz) 2800 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 2770 Architecture Folding Interpolating SNR (dB) 57 ENOB (Bits) 9.1 SFDR (dB) 70 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 1000, 2000 Resolution (Bits) 10 Number of input channels 1, 2 Interface type Parallel LVDS Analog input BW (MHz) 2800 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 2770 Architecture Folding Interpolating SNR (dB) 57 ENOB (Bits) 9.1 SFDR (dB) 70 Operating temperature range (°C) -40 to 85 Input buffer Yes
PBGA (NXA) 292 729 mm² 27 x 27
  • Excellent Accuracy and Dynamic Performance
  • Pin Compatible with ADC12D1000/1600/1800
  • Low Power Consumption, Further Reduced at Lower Fs
  • Internally Terminated, Buffered, Differential Analog Inputs
  • R/W SPI Interface for Extended Control Mode
  • Dual-Edge Sampling Mode, in Which the I- and Q-channels Sample One Input at Twice the Sampling Clock Rate
  • Test Patterns at Output for System Debug
  • Programmable 15-bit Gain and 12-bit Plus Sign Offset
  • Programmable tAD Adjust Feature
  • 1:1 Non-demuxed or 1:2 Demuxed LVDS Outputs
  • AutoSync Feature for Multi-Chip Systems
  • Single 1.9V ± 0.1V Power Supply
  • 292-Ball BGA Package (27mm x 27mm x 2.4mm with 1.27mm Ball-Pitch); No Heat Sink Required

All trademarks are the property of their respective owners.

  • Excellent Accuracy and Dynamic Performance
  • Pin Compatible with ADC12D1000/1600/1800
  • Low Power Consumption, Further Reduced at Lower Fs
  • Internally Terminated, Buffered, Differential Analog Inputs
  • R/W SPI Interface for Extended Control Mode
  • Dual-Edge Sampling Mode, in Which the I- and Q-channels Sample One Input at Twice the Sampling Clock Rate
  • Test Patterns at Output for System Debug
  • Programmable 15-bit Gain and 12-bit Plus Sign Offset
  • Programmable tAD Adjust Feature
  • 1:1 Non-demuxed or 1:2 Demuxed LVDS Outputs
  • AutoSync Feature for Multi-Chip Systems
  • Single 1.9V ± 0.1V Power Supply
  • 292-Ball BGA Package (27mm x 27mm x 2.4mm with 1.27mm Ball-Pitch); No Heat Sink Required

All trademarks are the property of their respective owners.

The ADC10D1000/1500 is the latest advance in TI's Ultra-High-Speed ADC family. This low-power, high-performance CMOS analog-to-digital converter digitizes signals at 10-bit resolution for dual channels at sampling rates of up to 1.0/1.5 GSPS (Non-DES Mode) or for a single channel up to 2.0/3.0 GSPS (DES Mode). The ADC10D1000/1500 achieves excellent accuracy and dynamic performance while dissipating less than 2.8/3.6 Watts. The product is packaged in a leaded or lead-free 292-ball thermally enhanced BGA package over the rated industrial temperature range of -40°C to +85°C.

The ADC10D1000/1500 builds upon the features, architecture and functionality of the 8-bit GHz family of ADCs. An expanded feature set includes AutoSync for multi-chip synchronization, 15-bit programmable gain and 12-bit plus sign programmable offset adjustment for each channel. The improved internal track-and-hold amplifier and the extended self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing 9.1/9.0 Effective Number of Bits (ENOB) with a 100 MHz input signal and a 1.0/1.5 GHz sample rate while providing a 10-18 Code Error Rate (CER) Dissipating a typical 2.77/3.59 Watts in Non-Demultiplex Mode at 1.0/1.5 GSPS from a single 1.9V supply, this device is specified to have no missing codes over the full operating temperature range.

Each channel has its own independent DDR Data Clock, DCLKI and DCLKQ, which are in phase when both channels are powered up, so that only one Data Clock could be used to capture all data, which is sent out at the same rate as the input sample clock. If the 1:2 Demux Mode is selected, a second 10-bit LVDS bus becomes active for each channel, such that the output data rate is sent out two times slower to relax data-capture timing requirements. The part can also be used as a single 2.0/3.0 GSPS ADC to sample one of the I or Q inputs. The output formatting can be programmed to be offset binary or two's complement and the Low Voltage Differential Signaling (LVDS) digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V to allow for power reduction for well-controlled back planes.

The ADC10D1000/1500 is the latest advance in TI's Ultra-High-Speed ADC family. This low-power, high-performance CMOS analog-to-digital converter digitizes signals at 10-bit resolution for dual channels at sampling rates of up to 1.0/1.5 GSPS (Non-DES Mode) or for a single channel up to 2.0/3.0 GSPS (DES Mode). The ADC10D1000/1500 achieves excellent accuracy and dynamic performance while dissipating less than 2.8/3.6 Watts. The product is packaged in a leaded or lead-free 292-ball thermally enhanced BGA package over the rated industrial temperature range of -40°C to +85°C.

The ADC10D1000/1500 builds upon the features, architecture and functionality of the 8-bit GHz family of ADCs. An expanded feature set includes AutoSync for multi-chip synchronization, 15-bit programmable gain and 12-bit plus sign programmable offset adjustment for each channel. The improved internal track-and-hold amplifier and the extended self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing 9.1/9.0 Effective Number of Bits (ENOB) with a 100 MHz input signal and a 1.0/1.5 GHz sample rate while providing a 10-18 Code Error Rate (CER) Dissipating a typical 2.77/3.59 Watts in Non-Demultiplex Mode at 1.0/1.5 GSPS from a single 1.9V supply, this device is specified to have no missing codes over the full operating temperature range.

Each channel has its own independent DDR Data Clock, DCLKI and DCLKQ, which are in phase when both channels are powered up, so that only one Data Clock could be used to capture all data, which is sent out at the same rate as the input sample clock. If the 1:2 Demux Mode is selected, a second 10-bit LVDS bus becomes active for each channel, such that the output data rate is sent out two times slower to relax data-capture timing requirements. The part can also be used as a single 2.0/3.0 GSPS ADC to sample one of the I or Q inputs. The output formatting can be programmed to be offset binary or two's complement and the Low Voltage Differential Signaling (LVDS) digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V to allow for power reduction for well-controlled back planes.

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Documentación técnica

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Tipo Título Fecha
* Data sheet ADC10D1000/1500 Low Power, 10-Bit, Dual 1.0/1.5 GSPS or Single 2.0/3.0 GSPS ADC datasheet (Rev. Q) 15 mar 2013
Application note AN-2132 Synchronizing Multiple GSPS ADCs in a System: The AutoSync Feature (Rev. G) 03 feb 2017
Application note Maximizing SFDR Performance in the GSPS ADC: Spur Sources and Methods of Mitigat 09 dic 2013
Application note AN-2128 ADC1xD1x00 Pin Compatibility (Rev. C) 01 may 2013
User guide Schematic and Layout Recommendations for the GSPS ADC 29 abr 2013
Application note AN-2177 Using the LMH6554 as a ADC Driver (Rev. A) 26 abr 2013
Application note From Sample Instant to Data Output: Understanding Latency in the GSPS ADC 18 dic 2012

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

ADC-LD-BB — Placa balun ADC de baja distorsión

One ADC-LD-BB board is included in the hardware kit with the GSPS analog-to-digital converter (ADC) reference boards. Since the analog inputs to the ADC1xDxx00RB are differential and most signal sources are single ended, these balun boards are generally used to achieve (...)

Guía del usuario: PDF
Soporte de software

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While WaveVision 5 software (...)

Productos y hardware compatibles

Productos y hardware compatibles

Productos
ADC de alta velocidad (≥ 10 MSPS)
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Desarrollo de hardware
Placa de evaluación
ADC12D1600RB Placa de referencia ADC de 12 bits, 1,6-/1,8 GSPS dobles o 3,2-/3,6 GSPS simples ADC16DV160HFEB Placa de evaluación ADC16DV160HFEB LM98640CVAL Interfaz analógica de doble canal, 14 bits y 40 MSPS con salida LVDS WAVEVSN-BRD-5.1 Placa de captura de datos WaveVision 5 (versión 5.1)
Software
Software de aplicación y estructura
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Modelo de simulación

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SNAM011.ZIP (83 KB) - IBIS Model
Herramienta de simulación

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Diseños de referencia

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Design guide: PDF
Esquema: PDF
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PBGA (NXA) 292 Ultra Librarian

Pedidos y calidad

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  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

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