ADC31JB68

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Convertidor analógico a digital (ADC) de 16 bits y 500 MSPS

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document-pdfAcrobat ADC31JB68 Single-channel, 16-bit, 500-MSPS analog-to-digital converter datasheet (Rev. B) (Inglés) PDF | HTML

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ADC31JB68

ACTIVO

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Detalles del producto

Sample rate (max) (Msps)

500

Resolution (Bits)

16

Number of input channels

1

Interface type

JESD204B

Analog input BW (MHz)

1300

Features

High Performance

Rating

Catalog

Peak-to-peak input voltage range (V)

1.7

Power consumption (typ) (mW)

915

Architecture

Pipeline

SNR (dB)

70.6

ENOB (Bits)

11.3

SFDR (dB)

83

Operating temperature range (°C)

-40 to 85

Input buffer

Yes

Sample rate (max) (Msps)

500

Resolution (Bits)

16

Number of input channels

1

Interface type

JESD204B

Analog input BW (MHz)

1300

Features

High Performance

Rating

Catalog

Peak-to-peak input voltage range (V)

1.7

Power consumption (typ) (mW)

915

Architecture

Pipeline

SNR (dB)

70.6

ENOB (Bits)

11.3

SFDR (dB)

83

Operating temperature range (°C)

-40 to 85

Input buffer

Yes

WQFN (RTA)

40

36 mm² (6 mm × 6 mm)

Single Channel
16-Bit Resolution
Maximum Clock Rate: 500 Msps
Small 40-Pin QFN Package (6 x 6 mm)
Input Buffer Input Bandwidth (3 dB): 1300 MHz
Aperture Jitter: 80 fs
On Chip Clock Divider: /1, /2, /4
On Chip Dither
Consistent Dynamic Performance Using Foreground and Background Calibration
Input Amplitude and Phase Adjustment
Input Full Scale: 1.7 Vpp
Power Supplies: 1.2/1.8/3 V
JESD204B Interface
- Subclass 1 Compliant
- 2 Lanes at 5 Gbps
Support for Multi-chip Synchronization
Key Specifications
- Power Dissipation: 915 mW at 500 Msps
- Performance at f_in = 210 MHz at –1 dBFS
  - SNR: 69.3 dBFS
  - NSD: –153.3 dBFS/Hz
  - SFDR: 80 dBc
  - Non-HD2,HD3: –91 dBFS
- Performance at fin = 450 MHz at –1 dBFS
  - SNR: 67 dBFS
  - NSD: –151 dBFS/Hz
  - SFDR: 77 dBc HD2,3
  - Non-HD2,HD3: –89 dBFS

Single Channel
16-Bit Resolution
Maximum Clock Rate: 500 Msps
Small 40-Pin QFN Package (6 x 6 mm)
Input Buffer Input Bandwidth (3 dB): 1300 MHz
Aperture Jitter: 80 fs
On Chip Clock Divider: /1, /2, /4
On Chip Dither
Consistent Dynamic Performance Using Foreground and Background Calibration
Input Amplitude and Phase Adjustment
Input Full Scale: 1.7 Vpp
Power Supplies: 1.2/1.8/3 V
JESD204B Interface
- Subclass 1 Compliant
- 2 Lanes at 5 Gbps
Support for Multi-chip Synchronization
Key Specifications
- Power Dissipation: 915 mW at 500 Msps
- Performance at f_in = 210 MHz at –1 dBFS
  - SNR: 69.3 dBFS
  - NSD: –153.3 dBFS/Hz
  - SFDR: 80 dBc
  - Non-HD2,HD3: –91 dBFS
- Performance at fin = 450 MHz at –1 dBFS
  - SNR: 67 dBFS
  - NSD: –151 dBFS/Hz
  - SFDR: 77 dBc HD2,3
  - Non-HD2,HD3: –89 dBFS

The ADC31JB68 is a low-power, wide-bandwidth, 16-bit, 500-MSPS analog-to-digital converter (ADC). The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy. This device is designed to sample input signals of up to 1.3 GHz.

The ADC31JB68 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very-low power consumption. On-chip dither provides an very-clean noise floor. Embedded foreground and background calibration provides consistent performance over the temperature range, and minimizes part-to-part variation.

This device supports the JESD204B serial interface with data rates up to 5 Gbps on each of two lanes, enabling high system integration density.

The ADC31JB68 comes in a 6-mm × 6-mm, 40-pin QFN package.

The ADC31JB68 is a low-power, wide-bandwidth, 16-bit, 500-MSPS analog-to-digital converter (ADC). The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy. This device is designed to sample input signals of up to 1.3 GHz.

The ADC31JB68 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very-low power consumption. On-chip dither provides an very-clean noise floor. Embedded foreground and background calibration provides consistent performance over the temperature range, and minimizes part-to-part variation.

This device supports the JESD204B serial interface with data rates up to 5 Gbps on each of two lanes, enabling high system integration density.

The ADC31JB68 comes in a 6-mm × 6-mm, 40-pin QFN package.

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Documentación principal	Tipo	Título	Opciones de formato	Descargar la versión más reciente en inglés	Fecha
*	Hoja de datos	ADC31JB68 Single-channel, 16-bit, 500-MSPS analog-to-digital converter datasheet (Rev. B)	PDF \| HTML		22/01/2019

Diseño y desarrollo

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Placa de evaluación

SDSP-3P-FMC-ADC500-5 — Módulo FMC-ADC500-5 de alto recuento de pines de Sundance Digital Signal Processing Inc.

FMC-ADC500-5 is a high pin count (HPC) FMC module with 5 ADC channels each running at up to 500MS/s with a dynamic range of 16 bits. The module has 5 ADC31JB68 ICs from Texas Instruments together with an HMC7044 from ADI which is the source of clocks feeding the ADCs. Provision for external clock (...)

Desde: Sundance Digital Signal Processing Inc.