Detalles del producto

Function Single-ended Additive RMS jitter (typ) (fs) 45 Output frequency (max) (MHz) 200 Number of outputs 10 Output supply voltage (V) 2.5, 3.3 Core supply voltage (V) 2.5, 3.3 Output skew (ps) 100 Features Pin control Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVTTL Input type LVTTL
Function Single-ended Additive RMS jitter (typ) (fs) 45 Output frequency (max) (MHz) 200 Number of outputs 10 Output supply voltage (V) 2.5, 3.3 Core supply voltage (V) 2.5, 3.3 Output skew (ps) 100 Features Pin control Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVTTL Input type LVTTL
TSSOP (PW) 24 49.92 mm² 7.8 x 6.4
  • High-Performance 1:10 Clock Driver
  • Operates up to 200 MHz at VDD 3.3 V
  • Pin-to-Pin Skew < 100 ps at VDD 3.3 V
  • VDD Range: 2.3 V to 3.6 V
  • Operating Temperature Range –40°C to 105°C
  • Supports 105ºC Ambient Temperature (see
    Thermal Considerations)
  • Output Enable Glitch Suppression
  • Distributes One Clock Input to Two Banks of Five
    Outputs
  • 25-Ω On-Chip Series Damping Resistors
  • Packaged in 24-Pin TSSOP
  • High-Performance 1:10 Clock Driver
  • Operates up to 200 MHz at VDD 3.3 V
  • Pin-to-Pin Skew < 100 ps at VDD 3.3 V
  • VDD Range: 2.3 V to 3.6 V
  • Operating Temperature Range –40°C to 105°C
  • Supports 105ºC Ambient Temperature (see
    Thermal Considerations)
  • Output Enable Glitch Suppression
  • Distributes One Clock Input to Two Banks of Five
    Outputs
  • 25-Ω On-Chip Series Damping Resistors
  • Packaged in 24-Pin TSSOP

The CDCVF2310 device is a high-performance, low-skew clock buffer that operates up to 200 MHz. Two banks of five outputs each provide low-skew copies of CLK. After power up, the default state of the outputs is low regardless of the state of the control pins. For normal operation, the outputs of bank 1Y[0:4] or 2Y[0:4] can be placed in a low state when the control pins (1G or 2G, respectively) are held low and a negative clock edge is detected on the CLK input. The outputs of bank 1Y[0:4] or 2Y[0:4] can be switched into the buffer mode when the control pins (1G and 2G) are held high and a negative clock edge is detected on the CLK input. The device operates in a 2.5-V and 3.3-V environment. The built-in output enable glitch suppression ensures a synchronized output enable sequence to distribute full period clock signals.

The CDCVF2310 is characterized for operation from –40°C to 85°C.

The CDCVF2310 device is a high-performance, low-skew clock buffer that operates up to 200 MHz. Two banks of five outputs each provide low-skew copies of CLK. After power up, the default state of the outputs is low regardless of the state of the control pins. For normal operation, the outputs of bank 1Y[0:4] or 2Y[0:4] can be placed in a low state when the control pins (1G or 2G, respectively) are held low and a negative clock edge is detected on the CLK input. The outputs of bank 1Y[0:4] or 2Y[0:4] can be switched into the buffer mode when the control pins (1G and 2G) are held high and a negative clock edge is detected on the CLK input. The device operates in a 2.5-V and 3.3-V environment. The built-in output enable glitch suppression ensures a synchronized output enable sequence to distribute full period clock signals.

The CDCVF2310 is characterized for operation from –40°C to 85°C.

Descargar Ver vídeo con transcripción Video

Documentación técnica

star =Principal documentación para este producto seleccionada por TI
No se encontraron resultados. Borre su búsqueda y vuelva a intentarlo.
Ver todo 2
Tipo Título Fecha
* Data sheet CDCVF2310 2.5-V to 3.3-V High-Performance Clock Buffer datasheet (Rev. D) PDF | HTML 30 oct 2015
Application note Using TI's CDCVF2310 and CDCVF25081 with TLK1501 Serial Transceiver 14 may 2003

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Modelo de simulación

CDCVF2310 IBIS Model (Rev. C)

SCAC026C.ZIP (33 KB) - IBIS Model
Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
TSSOP (PW) 24 Ultra Librarian

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Los productos recomendados pueden tener parámetros, módulos de evaluación o diseños de referencia relacionados con este producto de TI.

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

El contenido lo proporcionan “tal como está” TI y los colaboradores de la comunidad y no constituye especificaciones de TI. Consulte los términos de uso.

Si tiene preguntas sobre la calidad, el paquete o el pedido de productos de TI, consulte el soporte de TI. ​​​​​​​​​​​​​​

Videos