LMK1C1102A

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Búfer asíncrono de 1.8 V, 2.5 V o 3.3 V LVCMOS con salida de 2 canales

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Hoja de datos

document-pdfAcrobat LMK1C110xA 1.8V, 2.5V, and 3.3V Low Noise Asynchronous LVCMOS Clock Buffer Family datasheet (Inglés) PDF | HTML

LMK1C1102A

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Detalles del producto

Number of outputs

2

Additive RMS jitter (typ) (fs)

19.2

Core supply voltage (V)

1.8, 2.5, 3.3

Output supply voltage (V)

1.8, 2.5, 3.3

Output skew (ps)

25

Operating temperature range (°C)

-40 to 125

Rating

Catalog

Output type

LVCMOS

Input type

LVCMOS

Number of outputs

2

Additive RMS jitter (typ) (fs)

19.2

Core supply voltage (V)

1.8, 2.5, 3.3

Output supply voltage (V)

1.8, 2.5, 3.3

Output skew (ps)

25

Operating temperature range (°C)

-40 to 125

Rating

Catalog

Output type

LVCMOS

Input type

LVCMOS

WSON (DQF)

8

4 mm² (2 mm × 2 mm)

TSSOP (PW)

8

19.2 mm² (3 mm × 6.4 mm)

High-performance 1:2, 1:3, 1:4, 1:6 and 1:8 LVCMOS clock buffer
Very low output skew:
- LMK1C1102A, LMK1C1103A and LMK1C1104A < 50ps
- LMK1C1106 and LMK1C1108 < 55ps
Extremely low additive jitter:
- LMK1C1102A, LMK1C1103A and LMK1C1104A
  - 7.5fs typical at V_DD = 3.3V
  - 10fs typical at V_DD = 2.5V
  - 19.2fs typical at V_DD = 1.8V

LMK1C1106A and LMK1C1108A
- 12fs typical at VDD = 3.3V
- 15fs typical at VDD = 2.5V
- 28fs typical at VDD = 1.8V

Very low propagation delay < 3ns
Asynchronous output enable
Supply voltage: 3.3V, 2.5V, or 1.8V
- Fail-safe inputs: 3.3V tolerant input at all supply voltages
fmax = 250MHz for 3.3V fmax = 200MHz for 2.5V or 1.8V
Operating temperature range: –40°C to 125°C

High-performance 1:2, 1:3, 1:4, 1:6 and 1:8 LVCMOS clock buffer
Very low output skew:
- LMK1C1102A, LMK1C1103A and LMK1C1104A < 50ps
- LMK1C1106 and LMK1C1108 < 55ps
Extremely low additive jitter:
- LMK1C1102A, LMK1C1103A and LMK1C1104A
  - 7.5fs typical at V_DD = 3.3V
  - 10fs typical at V_DD = 2.5V
  - 19.2fs typical at V_DD = 1.8V

LMK1C1106A and LMK1C1108A
- 12fs typical at VDD = 3.3V
- 15fs typical at VDD = 2.5V
- 28fs typical at VDD = 1.8V

Very low propagation delay < 3ns
Asynchronous output enable
Supply voltage: 3.3V, 2.5V, or 1.8V
- Fail-safe inputs: 3.3V tolerant input at all supply voltages
fmax = 250MHz for 3.3V fmax = 200MHz for 2.5V or 1.8V
Operating temperature range: –40°C to 125°C

The LMK1C110xA is a modular, high-performance, low-skew, general-purpose clock buffer family from Texas Instruments. The entire family is designed with a modular approach in mind. Five different fan-out variations, 1:2, 1:3, 1:4, 1:6 and 1:8 are available.

All of the devices within this family are pin-compatible to each other and backwards compatible to the CDCLVC110x family for easy handling.

The LMK1C110xA supports a asynchronous output enable control (1G) which switches the outputs into a low state when 1G is low. Asynchronous enable and disable is helpful for 1PPS applications and DC inputs operations. These devices have a fail-safe input that prevents oscillation at the outputs in the absence of an input signal and allows for input signals before VDD is supplied.

The LMK1C110xA is a modular, high-performance, low-skew, general-purpose clock buffer family from Texas Instruments. The entire family is designed with a modular approach in mind. Five different fan-out variations, 1:2, 1:3, 1:4, 1:6 and 1:8 are available.

All of the devices within this family are pin-compatible to each other and backwards compatible to the CDCLVC110x family for easy handling.

The LMK1C110xA supports a asynchronous output enable control (1G) which switches the outputs into a low state when 1G is low. Asynchronous enable and disable is helpful for 1PPS applications and DC inputs operations. These devices have a fail-safe input that prevents oscillation at the outputs in the absence of an input signal and allows for input signals before VDD is supplied.

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Documentación principal	Tipo	Título	Opciones de formato	Descargar la versión más reciente en inglés		Fecha
*	Hoja de datos	LMK1C110xA 1.8V, 2.5V, and 3.3V Low Noise Asynchronous LVCMOS Clock Buffer Family datasheet	PDF \| HTML		27/05/2025

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Herramienta de diseño

PLLATINUMSIM-SW — Filtro de bucle PLL, ruido de fase, tiempo de bloqueo y herramienta de simulación de impulsos

PLLATINUMSIM-SW es una herramienta de simulación que permite a los usuarios crear diseños detallados y simulaciones de nuestros circuitos integrados PLLatinum™, que incluyen la serie LMX de bucles de bloqueo de fase (PLL) y sintetizadores.

Productos y hardware compatibles

Opciones de descarga

Encapsulado	Pines	Símbolos CAD, huellas y modelos 3D
WSON (DQF)	8	Ultra Librarian
TSSOP (PW)	8	Ultra Librarian

Se aplican los Términos y condiciones estándar de TI para los elementos de evaluación.

LMK1C1102A

Búfer asíncrono de 1.8 V, 2.5 V o 3.3 V LVCMOS con salida de 2 canales

LMK1C1102A

Detalles del producto

Documentación técnica

Diseño y desarrollo

PLLATINUMSIM-SW — Filtro de bucle PLL, ruido de fase, tiempo de bloqueo y herramienta de simulación de impulsos

Pedidos y calidad

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

Serie de videos

Videos