LMK5C33414AS1

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Sincronizador de red de cuatro entradas, 14 salidas, tres DPLL y tres APLL compatible con VCO de BAW

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document-pdfAcrobat LMK5C33414AS1 3-DPLL 3-APLL 4-IN 14-OUT Network Synchronizer With IEEE-1588 PTP Stack Software datasheet (Rev. A) (Inglés) PDF | HTML

LMK5C33414AS1

ACTIVO

Hoja de datos

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Detalles del producto

Operating temperature range (°C)

-40 to 105

Operating temperature range (°C)

-40 to 105

VQFN (RGC)

64

81 mm² (9 mm × 9 mm)

Ultra-low jitter BAW VCO based Wireless clocks
- 40fs typical/ 57fs maximum RMS jitter at 491.52MHz
- 50fs typical/ 62fs maximum RMS jitter at 245.76MHz
Three high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs)
- Programmable DPLL loop bandwidth from 1mHz to 4kHz
- < 1ppt DCO frequency adjustment step size
Four differential or single-ended DPLL inputs
- 1Hz (1PPS) to 800MHz input frequency
- Digital holdover and hitless switching
14 differential outputs with programmable HSDS, AC-LVPECL, LVDS, and HSCL formats
- Up to 18 total frequency outputs when configured with 6 LVCMOS frequency outputs on OUT[1:0]_P/N, GPIO1, and GPIO2 and 12 differential outputs on OUT[13:2]_P/N
- 1Hz (1PPS) to 1250MHz output frequency with programmable swing and common mode
- PCIe Gen 1 to 6 compliant
I2C, 3-wire SPI, or 4-wire SPI
–40°C to 85°C operating temperature

Ultra-low jitter BAW VCO based Wireless clocks
- 40fs typical/ 57fs maximum RMS jitter at 491.52MHz
- 50fs typical/ 62fs maximum RMS jitter at 245.76MHz
Three high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs)
- Programmable DPLL loop bandwidth from 1mHz to 4kHz
- < 1ppt DCO frequency adjustment step size
Four differential or single-ended DPLL inputs
- 1Hz (1PPS) to 800MHz input frequency
- Digital holdover and hitless switching
14 differential outputs with programmable HSDS, AC-LVPECL, LVDS, and HSCL formats
- Up to 18 total frequency outputs when configured with 6 LVCMOS frequency outputs on OUT[1:0]_P/N, GPIO1, and GPIO2 and 12 differential outputs on OUT[13:2]_P/N
- 1Hz (1PPS) to 1250MHz output frequency with programmable swing and common mode
- PCIe Gen 1 to 6 compliant
I2C, 3-wire SPI, or 4-wire SPI
–40°C to 85°C operating temperature

The LMK5C33414AS1 is a high-performance network synchronizer and jitter cleaner designed to meet the stringent requirements of wireless communications and infrastructure applications.

The device is bundled with software support for IEEE-1588 PTP synchronization to a primary reference clock source. For more information, contact TI.

The device integrates three DPLLs and three APLLs to provide hitless switching and jitter attenuation with programmable loop bandwidth (LBW) and one external loop filter capacitor, maximizing flexibility and ease of use.

APLL3 features an ultra-high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) technology. The BAW APLL can generate 491.52MHz output clocks with 40fs typical / 60fs maximum RMS jitter (12kHz to 20MHz) irrespective of the DPLL reference input frequency and jitter characteristics. APLL2 and APLL1 (conventional LC VCOs) provide options for a second or third frequency and/or synchronization domain.

Reference validation circuitry monitors the DPLL reference inputs and automatically performs a hitless switch when the inputs are detected or lost. Zero-Delay Mode (ZDM) provides control over the phase relationship between inputs and outputs.

The device is fully programmable through I2C or SPI. The integrated EEPROM can be used to customize system start-up clocks. The device also features factory default ROM profiles as fallback options.

The LMK5C33414AS1 is a high-performance network synchronizer and jitter cleaner designed to meet the stringent requirements of wireless communications and infrastructure applications.

The device is bundled with software support for IEEE-1588 PTP synchronization to a primary reference clock source. For more information, contact TI.

The device integrates three DPLLs and three APLLs to provide hitless switching and jitter attenuation with programmable loop bandwidth (LBW) and one external loop filter capacitor, maximizing flexibility and ease of use.

APLL3 features an ultra-high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) technology. The BAW APLL can generate 491.52MHz output clocks with 40fs typical / 60fs maximum RMS jitter (12kHz to 20MHz) irrespective of the DPLL reference input frequency and jitter characteristics. APLL2 and APLL1 (conventional LC VCOs) provide options for a second or third frequency and/or synchronization domain.

Reference validation circuitry monitors the DPLL reference inputs and automatically performs a hitless switch when the inputs are detected or lost. Zero-Delay Mode (ZDM) provides control over the phase relationship between inputs and outputs.

The device is fully programmable through I2C or SPI. The integrated EEPROM can be used to customize system start-up clocks. The device also features factory default ROM profiles as fallback options.

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Documentación principal	Tipo	Título	Opciones de formato	Descargar la versión más reciente en inglés	Fecha
*	Hoja de datos	LMK5C33414AS1 3-DPLL 3-APLL 4-IN 14-OUT Network Synchronizer With IEEE-1588 PTP Stack Software datasheet (Rev. A)	PDF \| HTML		5/02/2025

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Herramienta de diseño

CLOCK-PERFDATA-DESIGN — Clock performance data and register settings for clock generators, network synchronizers, jitter cleaners, and other clocking devices.

Configuration, raw phase noise data, noise plots, and register data for common use cases on clock generators, network synchronizers, jitter cleaners, and other clocking devices

Productos y hardware compatibles

Opciones de descarga

Encapsulado	Pines	Símbolos CAD, huellas y modelos 3D
VQFN (RGC)	64	Ultra Librarian

Se aplican los Términos y condiciones estándar de TI para los elementos de evaluación.

LMK5C33414AS1

Sincronizador de red de cuatro entradas, 14 salidas, tres DPLL y tres APLL compatible con VCO de BAW

LMK5C33414AS1

Detalles del producto

Documentación técnica

Diseño y desarrollo

CLOCK-PERFDATA-DESIGN — Clock performance data and register settings for clock generators, network synchronizers, jitter cleaners, and other clocking devices.

Pedidos y calidad

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

Serie de videos

Videos