LMKDB1108

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Búfer de reloj LP-HCSL de 8 salidas para interconexión de componentes periféricos express (PCle)

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Hoja de datos

document-pdfAcrobat LMKDB11xx PCIe Gen 1 to Gen 7 Ultra Low Jitter LP-HCSL Clock Buffer Family datasheet (Rev. G) (Inglés) PDF | HTML

LMKDB1108

ACTIVO

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Detalles del producto

Number of outputs

8

Additive RMS jitter (typ) (fs)

19.2

Core supply voltage (V)

1.8, 3.3

Output supply voltage (V)

1.8, 3.3

Output skew (ps)

50

Operating temperature range (°C)

-40 to 105

Rating

Catalog

Output type

LP-HCSL

Input type

LP-HCSL

Number of outputs

8

Additive RMS jitter (typ) (fs)

19.2

Core supply voltage (V)

1.8, 3.3

Output supply voltage (V)

1.8, 3.3

Output skew (ps)

50

Operating temperature range (°C)

-40 to 105

Rating

Catalog

Output type

LP-HCSL

Input type

LP-HCSL

VQFN (RKP)

40

25 mm² (5 mm × 5 mm)

LP-HCSL clock buffer and clock MUX that support:
- PCIe Gen 1 to Gen 7
- CC (Common Clock) and IR (Independent Reference) PCIe architectures
- Input clock with or without SSC
Intel DB2000QL and DB1206 compliant:
- All devices meet DB2000QL specifications
- LMKDB1120 is pin-compatible to DB2000QL
- LMKDB1112 is pin-compatible to DB1206
Extremely low additive jitter:
- 31fs maximum 12kHz to 20MHz RMS additive jitter at 156.25MHz
- 13fs maximum additive jitter for PCIe Gen 4
- 5fs maximum additive jitter for PCIe Gen 5
- 3fs maximum additive jitter for PCIe Gen 6
- 2.1fs maximum additive jitter for PCIe Gen 7
Fail-safe input
Fail-safe outputs (LMKDB1120FS, LMKDB1108FS and LMKDB1104FS only)
Flexible power-up sequence
Automatic output disable
Individual output enable
SBI (Side Band Interface) for high-speed output enable or disable
LOS (Loss of Signal) input detection
85Ω or 100Ω output impedance
1.8V / 3.3V ± 10% power supply
–40°C to 105°C ambient temperature

LP-HCSL clock buffer and clock MUX that support:
- PCIe Gen 1 to Gen 7
- CC (Common Clock) and IR (Independent Reference) PCIe architectures
- Input clock with or without SSC
Intel DB2000QL and DB1206 compliant:
- All devices meet DB2000QL specifications
- LMKDB1120 is pin-compatible to DB2000QL
- LMKDB1112 is pin-compatible to DB1206
Extremely low additive jitter:
- 31fs maximum 12kHz to 20MHz RMS additive jitter at 156.25MHz
- 13fs maximum additive jitter for PCIe Gen 4
- 5fs maximum additive jitter for PCIe Gen 5
- 3fs maximum additive jitter for PCIe Gen 6
- 2.1fs maximum additive jitter for PCIe Gen 7
Fail-safe input
Fail-safe outputs (LMKDB1120FS, LMKDB1108FS and LMKDB1104FS only)
Flexible power-up sequence
Automatic output disable
Individual output enable
SBI (Side Band Interface) for high-speed output enable or disable
LOS (Loss of Signal) input detection
85Ω or 100Ω output impedance
1.8V / 3.3V ± 10% power supply
–40°C to 105°C ambient temperature

The LMKDB devices are a family of extremely-low-jitter LP-HCSL buffers that support PCIe Gen 1 to Gen 7 and are DB2000QL compliant. The devices provide flexible power-up sequence, fail-safe inputs, fail-safe outputs, individual output active and inactive pins, loss of input signal (LOS) detection and automatic output disable features, as well as excellent power supply noise rejection performance.

Both 1.8V and 3.3V supply voltages are supported. For LMKDB1120, 1.8V power supply saves 250mW power compared to 3.3V.

The LMKDB devices are a family of extremely-low-jitter LP-HCSL buffers that support PCIe Gen 1 to Gen 7 and are DB2000QL compliant. The devices provide flexible power-up sequence, fail-safe inputs, fail-safe outputs, individual output active and inactive pins, loss of input signal (LOS) detection and automatic output disable features, as well as excellent power supply noise rejection performance.

Both 1.8V and 3.3V supply voltages are supported. For LMKDB1120, 1.8V power supply saves 250mW power compared to 3.3V.

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Documentación principal	Tipo	Título	Opciones de formato
*	Hoja de datos	LMKDB11xx PCIe Gen 1 to Gen 7 Ultra Low Jitter LP-HCSL Clock Buffer Family datasheet (Rev. G)	PDF \| HTML	29/05/2026
	Application brief	Mitigating FLEXIO Use Case Risks as Clock Pins Using LMKDB11xxFS Fail-safe Output Clock Buffers	PDF \| HTML	26/09/2025
	Nota sobre la aplicación	LMKDB1xxx PCI Express Compliance Report (Rev. A)	PDF \| HTML	22/04/2025
	Guía del usuario	RC19XXX, 9QXL2001X vs. LMKDB1XXX, CDCDB2000 Drop-In Replacement Guide.	PDF \| HTML	18/07/2024
	Nota sobre la aplicación	Clocking for PCIe Applications	PDF \| HTML	28/11/2023
	Nota sobre la aplicación	LMK6H and LMKDB1xxx PCI Express Compliance Report	PDF \| HTML	21/11/2023
	Informe	The Importance of Clocks in Data Centers	PDF \| HTML	21/11/2023
	Certificado	LMKDB1108EVM EU Declaration of Conformity (DoC)	PDF \| HTML	19/07/2023

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

LMKDB1108EVM — Módulo de evaluación LMKDB1108 para búfer de reloj de ocho salidas para PCIe Gen 1 a Gen 6

El módulo de evaluación (EVM) LMKDB1108 está diseñado para proporcionar una configuración rápida para evaluar el búfer LP-HCSL LMKDB1108 que admite PCIe Gen 1 a Gen 6 y es compatible con DB2000QL. La placa de circuito impreso (PCB) contiene varios puentes y una conexión USB para permitir al (...)

Guía del usuario: PDF | HTML

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Soporte de software

TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices

El software profesional de relojes y sintetizadores de Texas Instruments (TICS) p se utiliza para programar los módulos de evaluación (EVM) para números de producto con estos prefijos: CDC, LMK y LMX. Estos productos incluyen bucles de bloqueo de fase y osciladores controlados por tensión (...)

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